Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
Page 3 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
Page 4 General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
Page 5 Specification Differences between Products There are the following specification differences in these MCU products depending on the package. Table 1 Specification Differences Depending on Packages Specification Differences Chapter Products with 40 pins or less Products with 48 pins or more 9.
Page 6 Detailed descriptions of the CPU and instruction set RX Family R01US0032EJ Software User’s Manual: Software Application Note Examples of applications and sample programs — — Renesas Technical Preliminary report on the specifications of a product, — — Update document, etc.
Page 7 2. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. X.X.X ...
Page 8 3. List of Abbreviations and Acronyms Abbreviation Full Form ACIA Asynchronous Communications Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment Bus Input/Output IrDA Infrared Data Association...
Page 9: Table Of Contents
Contents Features ..............................32 Overview ............................33 Outline of Specifications ........................33 List of Products ............................ 37 Block Diagram ............................. 40 Pin Functions ............................41 Pin Assignments ..........................44 CPU ............................... 57 Features ..............................57 Register Set of the CPU ........................58 2.2.1 General-Purpose Registers (R0 to R15) ..................
Page 10 2.8.1 Overview ............................ 73 2.8.2 Instructions and Pipeline Processing ..................75 2.8.2.1 Instructions Converted into Single Micro-Operation and Pipeline Processing ....75 2.8.2.2 Instructions Converted into Multiple Micro-Operations and Pipeline Processing .... 77 2.8.2.3 Pipeline Basic Operation ....................80 2.8.3 Calculation of the Instruction Processing Time .................
Page 11 7.2.2 Option Function Select Register 1 (OFS1) ................120 7.2.3 Endian Select Register (MDE) ....................122 Usage Note ............................123 7.3.1 Setting Example of Option-Setting Memory ................123 7.3.2 Note on Parallel Use of the Voltage Monitoring 1 Reset and IWDT Reset ......123 Voltage Detection Circuit (LVDAa) ....................
Page 12 9.3.3 Handling of Pins When the Main Clock is Not Used ............... 158 9.3.4 Notes on the External Clock Input ................... 158 Sub-Clock Oscillator ......................... 159 9.4.1 Connecting 32.768-kHz Crystal ....................159 9.4.2 Handling of Pins When Sub-Clock is Not Used ............... 159 Oscillation Stop Detection Function ....................
Page 13 11.2.2 Module Stop Control Register A (MSTPCRA) ................ 184 11.2.3 Module Stop Control Register B (MSTPCRB) ................ 185 11.2.4 Module Stop Control Register C (MSTPCRC) ................ 186 11.2.5 Operating Power Control Register (OPCCR) ................187 11.2.6 Sub Operating Power Control Register (SOPCCR) ..............188 11.2.7 Sleep Mode Return Clock Source Switching Register (RSTCKCR) ........
Page 14 13.3 Acceptance of Exception Events ....................... 211 13.3.1 Acceptance Timing and Saved PC Value ................. 211 13.3.2 Vector and Site for Saving the Values in the PC and PSW ............211 13.4 Hardware Processing for Accepting and Returning from Exceptions ..........212 13.5 Hardware Pre-Processing ........................
Page 15 14.4.4 Determining Priority ......................... 245 14.4.5 Multiple Interrupts ........................245 14.4.6 Fast Interrupt ..........................246 14.4.7 Digital Filter ..........................246 14.4.8 External Pin Interrupts ......................247 14.5 Non-maskable Interrupt Operation ....................248 14.6 Return from Power-Down States ....................... 249 14.6.1 Return from Sleep Mode or Deep Sleep Mode ................
Page 16 16.2.6 DTC Transfer Count Register B (CRB) ................... 268 16.2.7 DTC Control Register (DTCCR) ....................268 16.2.8 DTC Vector Base Register (DTCVBR) ................... 269 16.2.9 DTC Address Mode Register (DTCADMOD) ................. 269 16.2.10 DTC Module Start Register (DTCST) ..................270 16.2.11 DTC Status Register (DTCSTS) ....................
Page 17 17.5 Handling of Unused Pins ........................309 Multi-Function Pin Controller (MPC) .................... 310 18.1 Overview ............................310 18.2 Register Descriptions ......................... 315 18.2.1 Write-Protect Register (PWPR) ....................315 18.2.2 P1n Pin Function Control Register (P1nPFS) (n = 4 to 7) ............316 18.2.3 P2n Pin Function Control Register (P2nPFS) (n = 6 to 7) ............
Page 18 19.3.5 PWM Modes ..........................378 19.3.6 Phase Counting Mode ....................... 382 19.3.7 External Pulse Width Measurement ..................388 19.3.8 Noise Filter ..........................389 19.4 Interrupt Sources ..........................390 19.4.1 Interrupt Sources and Priorities ....................390 19.4.2 DTC Activation ........................391 19.4.3 A/D Converter Activation ......................
Page 19 20.2.4 Compare Match Constant Register (CMCOR) ................. 425 20.3 Operation ............................426 20.3.1 Periodic Count Operation ......................426 20.3.2 CMCNT Count Timing ......................426 20.4 Interrupts ............................427 20.4.1 Interrupt Sources ........................427 20.4.2 Timing of Compare Match Interrupt Generation ..............427 20.5 Usage Notes ............................
Page 20 21.3.6 Alarm Function ......................... 457 21.3.7 Procedure for Disabling Alarm Interrupt .................. 458 21.3.8 Time Error Adjustment Function ..................... 458 21.3.8.1 Automatic Adjustment ..................... 458 21.3.8.2 Adjustment by Software ....................459 21.3.8.3 Procedure for Changing the Mode of Adjustment ............460 21.3.8.4 Procedure for Stopping Adjustment ................
Page 21 Serial Communications Interface (SCIe, SCIf) ................485 23.1 Overview ............................485 23.2 Register Descriptions ......................... 491 23.2.1 Receive Shift Register (RSR) ....................491 23.2.2 Receive Data Register (RDR) ....................491 23.2.3 Transmit Data Register (TDR) ....................491 23.2.4 Transmit Shift Register (TSR) ....................491 23.2.5 Serial Mode Register (SMR) ....................
Page 22 23.3.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ....536 23.3.3 Clock ............................537 23.3.4 CTS and RTS Functions ......................537 23.3.5 SCI Initialization (Asynchronous Mode) ................. 538 23.3.6 Serial Data Transmission (Asynchronous Mode) ..............539 23.3.7 Serial Data Reception (Asynchronous Mode) ................
Page 23 23.9.2 Transmitting a Start Frame ....................... 588 23.9.3 Receiving a Start Frame ......................591 23.9.3.1 Priority Interrupt Bit ......................596 23.9.4 Detection of Bus Collisions ...................... 597 23.9.5 Digital Filter for Input on the RXDX12 Pin ................598 23.9.6 Bit Rate Measurement ......................599 23.9.7 Selectable Timing for Sampling Data Received through RXDX12 .........
Page 24 24.2.7 C-bus Status Enable Register (ICSER) ................. 633 24.2.8 C-bus Interrupt Enable Register (ICIER) ................635 24.2.9 C-bus Status Register 1 (ICSR1) ................... 637 24.2.10 C-bus Status Register 2 (ICSR2) ................... 640 24.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2) ..............643 24.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2) ..............
Page 25 24.11.2 Extra SCL Clock Cycle Output Function ................. 687 24.11.3 RIIC Reset and Internal Reset ....................688 24.12 SMBus Operation ..........................689 24.12.1 SMBus Timeout Measurement ....................689 24.12.2 Packet Error Code (PEC) ......................690 24.12.3 SMBus Host Notification Protocol (Notify ARP Master Command) ........690 24.13 Interrupt Sources ..........................
Page 26 25.3.4 Data Format ..........................727 25.3.4.1 When Parity is Disabled (SPCR2.SPPE = 0) ..............728 25.3.4.2 When Parity is Enabled (SPCR2.SPPE = 1) ..............732 25.3.5 Transfer Format ........................736 25.3.5.1 CPHA = 0 ........................736 25.3.5.2 CPHA = 1 ........................737 25.3.6 Communications Operating Mode ....................
Page 27 12-Bit A/D Converter (S12ADb) ....................778 27.1 Overview ............................778 27.2 Register Descriptions ......................... 782 27.2.1 A/D Data Registers y (ADDRy) (y = 0 to 4, 6, 8 to 15) ............782 27.2.2 A/D Data Duplication Register (ADDBLDR) ................784 27.2.3 A/D Temperature Sensor Data Register (ADTSDR) ...............
Page 28 27.6.4 Notes on Scan End Interrupt Handling ..................812 27.6.5 Module Stop Function Setting ....................812 27.6.6 Notes on Entering Low Power Consumption States ..............812 27.6.7 Notes on Releasing Software Standby Mode ................812 27.6.8 Allowable Impedance of Signal Source ................... 813 27.6.9 Influence on Absolute Accuracy ....................
Page 29 31.3.2 Protection Unlock Register (FPR) .................... 833 31.3.3 Protection Unlock Status Register (FPSR) ................833 31.3.4 Flash P/E Mode Control Register (FPMCR) ................834 31.3.5 Flash Initial Setting Register (FISR) ..................835 31.3.6 Flash Reset Register (FRESETR) ..................... 837 31.3.7 Flash Area Select Register (FASR) ..................
Page 30 31.6.5 Interrupt ............................ 861 31.7 Boot Mode ............................862 31.7.1 Boot Mode (SCI) ........................862 31.7.1.1 System Configuration in Boot Mode (SCI) ..............862 31.7.1.2 Starting Up in Boot Mode (SCI) ..................865 31.7.2 Boot Mode (FINE Interface) ....................866 31.7.2.1 Operating Conditions in Boot Mode (FINE Interface) ............
Page 31 31.9.9.3 Procedure to Select the Device and Change the Bit Rate ..........890 31.9.9.4 Transition to the Program/Erase State ................891 31.9.9.5 Unlock Boot Mode ID Code Protection ................892 31.9.9.6 Erase Ready Operation ....................893 31.9.9.7 Erase the User Area ......................894 31.9.9.8 Program the User Area ....................
Page 32: Features
RX110 Group R01UH0421EJ0120 Rev.1.20 Renesas MCUs Jul 29, 2016 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory, up to 5 comms channels, 12-bit A/D, RTC Features PLQP0064KB-A 10 × 10 mm, 0.5 mm pitch ■...
Page 33: Overview
RX110 Group 1. Overview Overview Outline of Specifications Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different packages. Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the package type.
Page 34 RX110 Group 1. Overview Table 1.1 Outline of Specifications (2/3) Classification Module/Function Description I/O ports General I/O ports 64-pin /48-pin /40-pin /36-pin  I/O: 50/34/28/24  Input: 2/2/1/1  Pull-up resistors: 42/28/23/20  Open-drain outputs: 38/28/23/20  5-V tolerance: 4/4/4/4 Multi-function pin controller (MPC) Capable of selecting the input/output function from multiple pins ...
Page 35 RX110 Group 1. Overview Table 1.1 Outline of Specifications (3/3) Classification Module/Function Description Data operation circuit (DOC) Comparison, addition, and subtraction of 16-bit data Unique ID 32-byte ID code for the MCU Power supply voltages/Operating frequencies VCC = 1.8 to 2.4 V: 8 MHz, VCC = 2.4 to 2.7 V: 16 MHz, VCC = 2.7 to 3.6 V: 32 MHz Supply current 3.2 mA at 32 MHz (typ.) D version: 40 to +85°C, G version: 40 to +105°C...
Page 36 RX110 Group 1. Overview Table 1.2 Comparison of Functions for Different Packages RX110 Group Module/Functions 64 Pins 48 Pins 40 Pins 36 Pins Interrupts External interrupts NMI, IRQ0 to IRQ7 Data transfer controller Supported Timers Multi-function timer pulse unit 2 4 channels (MTU0 to MTU2, MTU5) Compare match timer 2 channels ×...
Page 37: List Of Products
RX110 Group 1. Overview List of Products Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no., memory capacity, and package type. Table 1.3 List of Products (1/2) Maximum Operating Operating Group Part No.
Page 38 PWQN0040KC-A Note: Orderable part numbers are current as of when this manual was published. Please make sure to refer to the relevant product page on the Renesas website for the latest part numbers. R01UH0421EJ0120 Rev.1.20 Page 38 of 968 Jul 29, 2016...
Page 39 11: RX111 Group Series name RX100 Series Type of memory F: Flash memory version Renesas MCU Renesas semiconductor product Figure 1.1 How to Read the Product Part No., Memory Capacity, and Package Type R01UH0421EJ0120 Rev.1.20 Page 39 of 968 Jul 29, 2016...
Page 40: Block Diagram
RX110 Group 1. Overview Block Diagram Figure 1.2 shows a block diagram IWDTa SCIe × 2 channels SCIf × 1 channel RSPI × 1 channel Port 0 RIIC × 1 channel Port 1 ICUb MTU2b × 4 channels Port 2 CMT ×...
Page 41: Pin Functions
RX110 Group 1. Overview Pin Functions Table 1.4 lists the pin functions. Table 1.4 Pin Functions (1/3) Classifications Pin Name Description Power supply Input Power supply pin. Connect it to the system power supply. Connect this pin to the VSS pin via the 4.7 μF smoothing capacitor used to —...
Page 42 RX110 Group 1. Overview Table 1.4 Pin Functions (2/3) Classifications Pin Name Description  Simple I Serial C mode communications SSCL1, SSCL5 Input/output pins for the I C clock. interface (SCIe) SSDA1, SSDA5 Input/output pins for the I C data. ...
Page 43 RX110 Group 1. Overview Table 1.4 Pin Functions (3/3) Classifications Pin Name Description I/O ports PC0 to PC7 8-bit input/output pins. PE0 to PE7 8-bit input/output pins. PH0 to PH3 4-bit input/output pins. Input 1-bit input pin. PJ6, PJ7 2-bit input/output pins. Note 1.
Page 44: Pin Assignments
RX110 Group 1. Overview Pin Assignments Figure 1.3 to Figure 1.7 show the pin assignments. Table 1.5 to Table 1.9 show the lists of pins and pin functions. RX110 Group PLQP0064KB-A PLQP0064GA-A (64-pin LFQFP/LQFP) PJ7/VREFL0 (Top view) PJ6/VREFH0 AVSS0 AVCC0 Note: This figure indicates the power supply pins and I/O ports.
Page 45 RX110 Group 1. Overview RX110 Group PWLG0064KA-A (64-pin WFLGA) (Upper perspective view) PJ7/ VREFL0 PJ6/ VREFH0 AVCC0 PH7/ AVSS0 XCOUT RES# XTAL EXTAL XCIN Note: This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (64-Pin WFLGA)”. Note: For the position of A1 pin in the package, see “Package Dimensions”.
Page 46 RX110 Group 1. Overview Group RX110 PLQP0048KB-A (48-pin LFQFP) PJ7/VREFL0 (Top view) PJ6/VREFH0 AVSS0 AVCC0 Group RX110 PWQN0048KB-A (48-pin HWQFN) PJ7/VREFL0 (Top view) PJ6/VREFH0 AVSS0 AVCC0 Note: This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (48-Pin LFQFP/HWQFN)”. Note: It is recommended that the exposed die pad of HWQFN should be connected to VSS .
Page 47 RX110 Group 1. Overview RX110 Group PWQN0040KC-A (40-pin HWQFN) PJ7/VREFL0 (Top view) PJ6/VREFH0 AVSS0 AVCC0 Note: This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (40-Pin HWQFN)”. Note: It is recommended that the exposed die pad of HWQFN should be connected to VSS.
Page 48 RX110 Group 1. Overview RX110 Group PWLG0036KA-A (36-pin WFLGA) (Upper perspective view) PJ6/ PJ7/ VREFH0 VREFL0 AVCC0 AVSS0 RES# XTAL EXTAL Note: This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the table “List of Pins and Pin Functions (36-Pin WFLGA)”. Note: For the position of A1 pin in the package, see “Package Dimensions”.
Page 49 RX110 Group 1. Overview Table 1.5 List of Pins and Pin Functions (64-Pin LFQFP/LQFP) (1/2) Power Supply, Clock, Communication System Control I/O Port Timers (MTU, RTC) (SCIe, SCIf, RSPI, RIIC) Others MTIOC2B SCK1/SCK12 IRQ3/CMPA2/ CACREF/ADTRG0# MTIOC2A TXD1/SMOSI1/SSDA1 RXD1/SMISO1/SSCL1 IRQ0 CTS1#/RTS1#/SS1# IRQ1 FINED RES#...
Page 50 RX110 Group 1. Overview Table 1.5 List of Pins and Pin Functions (64-Pin LFQFP/LQFP) (2/2) Power Supply, Clock, Communication System Control I/O Port Timers (MTU, RTC) (SCIe, SCIf, RSPI, RIIC) Others SSLA1 CACREF MTIOC2B IRQ5/AN013 MTIOC1A MOSIA IRQ4/AN012 MTIOC0A/MTIOC1B CTS12#/RTS12#/SS12#/RSPCKA IRQ3/AN011 RXD12/RXDX12/SMISO12/SSCL12 IRQ7/AN010...
Page 51 RX110 Group 1. Overview Table 1.6 List of Pins and Pin Functions (64-Pin WFLGA) (1/2) Power Supply, Clock, Communication System Control I/O Port Timers (MTU, RTC) (SCIe, SCIf, RSPI, RIIC) Others AVSS0 AVCC0 VREFH0 PJ6* VREFL0 PJ7* P43* AN003 P46* AN006 RXD12/RXDX12/SMISO12/SSCL12 IRQ7/AN010...
Page 52 RX110 Group 1. Overview Table 1.6 List of Pins and Pin Functions (64-Pin WFLGA) (2/2) Power Supply, Clock, Communication System Control I/O Port Timers (MTU, RTC) (SCIe, SCIf, RSPI, RIIC) Others MTCLKB TXD1/SMOSI1/SSDA1/MISOA CACREF MTCLKC SCK5/SSLA0 IRQ2/CLKOUT MTIOC1B/MTIOC2A MTIOC0C SCK1/MISOA/SDA0/RXD12/RXDX12/ IRQ7 SMISO12/SSCL12 RTCOUT...
Page 53 RX110 Group 1. Overview Table 1.7 List of Pins and Pin Functions (48-Pin LFQFP/HWQFN) (1/2) Power Supply, Clock, Communication System Control I/O Port Timers (MTU, RTC) (SCIe, SCIf, RSPI, RIIC) Others MTIOC2B SCK1/SCK12 IRQ3/CMPA2/ CACREF/ADTRG0# MTIOC2A TXD1/SMOSI1/SSDA1 FINED RES# XCOUT XCIN XTAL EXTAL...
Page 54 RX110 Group 1. Overview Table 1.7 List of Pins and Pin Functions (48-Pin LFQFP/HWQFN) (2/2) Power Supply, Clock, Communication System Control I/O Port Timers (MTU, RTC) (SCIe, SCIf, RSPI, RIIC) Others P40* AN000 VREFH0 PJ6* AVSS0 AVCC0 Note 1. The power source of the I/O buffer for these pins is AVCC0. R01UH0421EJ0120 Rev.1.20 Page 54 of 968 Jul 29, 2016...
Page 55 RX110 Group 1. Overview Table 1.8 List of Pins and Pin Functions (40-Pin HWQFN) Power Supply, Clock, Communication System Control I/O Port Timers (MTU, RTC) (SCIe, SCIf, RSPI, RIIC) Others MTIOC2B SCK1/SCK12 IRQ3/CMPA2/ CACREF/ADTRG0# MTIOC2A TXD1/SMOSI1/SSDA1 FINED RES# XTAL EXTAL MTIOC0C IRQ2 MTIOC0C...
Page 56 RX110 Group 1. Overview Table 1.9 List of Pins and Pin Functions (36-Pin WFLGA) Power Supply, Clock, Communication System Control I/O Port Timers (MTU, RTC) (SCIe, SCIf, RSPI, RIIC) Others AVSS0 AVCC0 VREFH0 PJ6* P42* AN002 P41* AN001 RXD12/RXDX12/SMISO12/SSCL12 IRQ7/AN010 RES# MTIOC2B SCK1/SCK12...
Page 57: Cpu
RX110 Group 2. CPU This MCU has the RX CPU as its core. A variable-length instruction format has been adopted for the RX CPU. Allocating the more frequently used instructions to the shorter instruction lengths facilitates the development of efficient programs that take up less memory. The CPU has 73 basic instructions and nine DSP instructions, for a total of 82 instructions.
Page 58: Register Set Of The Cpu
RX110 Group 2. CPU Register Set of the CPU The RX CPU has 16 general-purpose registers, eight control registers, and one accumulator used for DSP instructions. General-purpose registers R0 (SP) Control registers (Interrupt stack pointer) (User stack pointer) INTB (Interrupt table register) (Program counter) (Processor status word) (Backup PC)
Page 59: General-Purpose Registers (R0 To R15)
RX110 Group 2. CPU 2.2.1 General-Purpose Registers (R0 to R15) This CPU has 16 general-purpose registers (R0 to R15). R0 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW).
Page 60: Interrupt Stack Pointer (Isp)/User Stack Pointer (Usp)
RX110 Group 2. CPU 2.2.2.1 Interrupt Stack Pointer (ISP)/User Stack Pointer (USP) Value after reset: Value after reset: The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP). Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the processor status word (PSW).
Page 61: Processor Status Word (Psw)
RX110 Group 2. CPU 2.2.2.4 Processor Status Word (PSW) — — — — IPL[3:0] — — — — — Value after reset: — — — — — — — — — — — — Value after reset: Symbol Bit Name Description Carry Flag 0: No carry has occurred.
Page 62: Backup Pc (Bpc)
RX110 Group 2. CPU The processor status word (PSW) indicates the results of instruction execution or the state of the CPU. C Flag (Carry Flag) This flag indicates whether a carry, borrow, or shift-out has occurred as the result of an operation. Z Flag (Zero Flag) This flag indicates that the result of an operation was 0.
Page 63: Backup Psw (Bpsw)
RX110 Group 2. CPU 2.2.2.6 Backup PSW (BPSW) Value after reset: Undefined The backup PSW (BPSW) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The allocation of bits in the BPSW corresponds to that in the PSW.
Page 64: Processor Mode
RX110 Group 2. CPU Processor Mode The RX CPU supports two processor modes, supervisor and user. These processor modes enable the realization of a hierarchical CPU resource protection. Each processor mode imposes a level on rights of access to the CPU resources and the instructions that can be executed. Supervisor mode carries greater rights than those of user mode.
Page 65: Data Types
RX110 Group 2. CPU Data Types The RX CPU can handle three types of data: integer, bit, and string. For details, refer to RX Family User's Manual: Software. Endian For the RX CPU, instructions are little endian, but the data arrangement is selectable as little or big endian. 2.5.1 Switching the Endian As arrangements of bytes, this MCU supports both big endian, where the higher-order byte (MSB) is at location 0, and...
Page 66 RX110 Group 2. CPU Table 2.3 32-Bit Write Operations when Little Endian has been Selected Operation Address Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit of dest to address 0 to address 1 to address 2 to address 3...
Page 67 RX110 Group 2. CPU Table 2.6 16-Bit Read Operations when Big Endian has been Selected Operation Reading Reading Reading Reading Reading Reading Reading Address a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from...
Page 68 RX110 Group 2. CPU Table 2.10 8-Bit Read Operations when Big Endian has been Selected Operation Reading an 8-bit unit from Reading an 8-bit unit from Reading an 8-bit unit from Reading an 8-bit unit from Address of src address 0 address 1 address 2 address 3...
Page 69: Access To I/O Registers
RX110 Group 2. CPU 2.5.2 Access to I/O Registers The addresses of I/O registers are fixed, and this is regardless of whether the setting is for little endian or big endian. Accordingly, changes to the endian do not affect access to I/O registers. For the arrangements of I/O registers, refer to the descriptions of registers in the relevant sections.
Page 70: Data Arrangement In Memory
RX110 Group 2. CPU 2.5.4.2 Data Arrangement in Memory Data in memory have three sizes: byte (8-bit), word (16-bit), and longword (32-bit). The data arrangement is selectable as little endian or big endian. Figure 2.3 shows the arrangement of data in memory. Data type Address Data image...
Page 71: Vector Table
RX110 Group 2. CPU Vector Table There are two types of vector table: fixed and relocatable. Each vector in the vector table consists of 4 bytes and specifies the address where the corresponding exception handling routine starts. 2.6.1 Fixed Vector Table The fixed vector table is allocated to a fixed address range.
Page 72: Relocatable Vector Table
RX110 Group 2. CPU 2.6.2 Relocatable Vector Table The address where the relocatable vector table is placed can be adjusted. The table is a 1,024-byte region that contains all vectors for unconditional traps and interrupts and starts at the address (IntBase) specified in the interrupt table register (INTB).
Page 73: Operation Of Instructions
RX110 Group 2. CPU Operation of Instructions 2.7.1 Data Prefetching by the RMPA Instruction and the String-Manipulation Instructions The RMPA instruction and the string-manipulation instructions except the SSTR instruction (that is, SCMPU, SMOVB, SMOVF, SMOVU, SUNTIL, and SWHILE instructions) may prefetch data from the memory to speed up the read processing.
Page 74 RX110 Group 2. CPU (5) WB stage (write-back stage) The operation result and the data read from memory are written to the register (RW) in the WB stage. The data read from memory and the other type of data, such as the operation result, can be written to the register in the same clock cycles. Figure 2.6 shows the pipeline configuration and its operation.
Page 75: Instructions And Pipeline Processing
RX110 Group 2. CPU 2.8.2 Instructions and Pipeline Processing The operands in the table below indicate the following meaning. #IMM: Immediate flag: bit, flag Rs, Rs2, Rd, Rd2, Ri, Rb: General-purpose register CR: Control register dsp: displacement pcdsp: displacement 2.8.2.1 Instructions Converted into Single Micro-Operation and Pipeline Processing The table below lists the instructions that are converted into a single micro-operation.
Page 76 RX110 Group 2. CPU Figure 2.7 to Figure 2.9 show the operation of instructions that are converted into a basic single micro-operation. 4 stages ADD R1, R2 Note: Multi-cycle instructions (DIV, DIVU) are executed in multiple cycles in the E stage. DIV R3, R4 Figure 2.7 Operation for Register-Register, Immediate-Register...
Page 77: Instructions Converted Into Multiple Micro-Operations And Pipeline Processing
RX110 Group 2. CPU 2.8.2.2 Instructions Converted into Multiple Micro-Operations and Pipeline Processing The table below lists the instructions that are converted into multiple micro-operations. The number of cycles in the table indicates the number of cycles during no-wait memory access. Table 2.14 Instructions that are Converted into Multiple Micro-Operations (1/2) Mnemonic (indicates the common operation when...
Page 78 RX110 Group 2. CPU Table 2.14 Instructions that are Converted into Multiple Micro-Operations (2/2) Mnemonic (indicates the common operation when Reference Instruction the size is omitted) Figure Number of Cycles  SCMPU String manipulation instructions* — 2+4×floor(n/4)+4×(n%4) n: Number of comparison bytes* ...
Page 79 RX110 Group 2. CPU Figure 2.10 to Figure 2.14 show the operation of instructions that are converted into basic multiple micro-operations. Note: mop: Micro-operation, stall: Pipeline stall Bypass process ADD [R1], R2 (mop1) load stall (mop2) add Figure 2.10 Arithmetic/Logic Instruction (Memory Source Operand) Load data Bit manipulation, store operation...
Page 80: Pipeline Basic Operation
RX110 Group 2. CPU 2.8.2.3 Pipeline Basic Operation In the ideal pipeline processing, each stage is executed in one cycle, though all instructions may not be pipelined in due to the processing in each stage and the branch execution. The CPU controls the pipeline stage with the IF stage in the unit of instructions, while the D and subsequent stages in the unit of micro-operations.
Page 81 RX110 Group 2. CPU (2) Pipeline Flow with no Stall (a) Bypass process Even when the result of the preceding instruction will be used in a subsequent instruction, the operation processing between registers is pipelined in by the bypass process. ADD R1, R2 (mop) add Bypass process...
Page 82: Calculation Of The Instruction Processing Time
RX110 Group 2. CPU (d) When the load data is not used by the subsequent instruction When the load data is not used by the subsequent instruction, the subsequent operations are in fact executed earlier and the operation processing ends (out-of-order completion). (mop) load MOV [R1], R2 (mop) add...
Page 83: Numbers Of Cycles For Response To Interrupts
RX110 Group 2. CPU 2.8.4 Numbers of Cycles for Response to Interrupts Table 2.15 lists numbers of cycles taken by processing for response to interrupts. Table 2.15 Numbers of Cycles for Response to Interrupts Type of Interrupt Request/Details of Processing Fast Interrupt Other Interrupts 2 cycles...
Page 84: Operating Modes
RX110 Group 3. Operating Modes Operating Modes Operating Mode Types and Selection Operating modes are selected by the pin level when a reset is released. Table 3.1 shows the relationship between levels on the mode setting pins (MD) on release from the reset state and the operating mode selected at that time.
Page 85: Register Descriptions
RX110 Group 3. Operating Modes Register Descriptions 3.2.1 Mode Monitor Register (MDMONR) Address(es): 0008 0000h — — — — — — — — — — — — — — — Value after reset: 0/1* Note 1. Depends on the setting of the mode pin (MD). When the MD pin is low, the bit value is 0; otherwise, the bit value is 1. Symbol Bit Name Description...
Page 86: System Control Register 1 (Syscr1)
RX110 Group 3. Operating Modes 3.2.2 System Control Register 1 (SYSCR1) Address(es): 0008 0008h — — — — — — — — — — — — — — — RAME Value after reset: Symbol Bit Name Description RAME RAM Enable 0: The RAM is disabled.
Page 87: Details Of Operating Modes
RX110 Group 3. Operating Modes Details of Operating Modes 3.3.1 Single-Chip Mode In this mode, all I/O ports can be used as general input/output ports, peripheral function input/output, or interrupt input pins. The chip starts up in single-chip mode if the high level is on the MD pin on release from the reset state. 3.3.2 Boot Mode In this mode, the on-chip flash memory modifying program (boot program) stored in a dedicated area within the MCU...
Page 88: Address Space
RX110 Group 4. Address Space Address Space Address Space This MCU has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is, linear access to an address space of up to 4 Gbytes is possible, and this contains program area. Figure 4.1 shows the memory map.
Page 89 RX110 Group 4. Address Space Single-chip mode* 0000 0000h RAM* 0000 4000h Reserved area* 0008 0000h Peripheral I/O registers 0010 0000h Reserved area* 007F C000h Peripheral I/O registers 007F C500h Reserved area* 007F FC00h Peripheral I/O registers 0080 0000h Reserved area* FFFE 0000h On-chip ROM (program ROM)* FFFF FFFFh...
Page 90: I/O Registers
RX110 Group 5. I/O Registers I/O Registers This section provides information on the on-chip I/O register addresses and bit configuration. The information is given as shown below. Notes on writing to I/O registers are also given below. (1) I/O register addresses (address order) ...
Page 91 RX110 Group 5. I/O Registers  Longword-size I/O registers MOV.L #SFR_ADDR, R1 MOV.L #SFR_DATA, [R1] [R1].L, R1 ;; Next process When executing an instruction after writing to multiple registers, only read the last I/O register written to and execute the instruction using that value;...
Page 92: I/O Register Addresses (Address Order)
RX110 Group 5. I/O Registers I/O Register Addresses (Address Order) Table 5.1 List of I/O Registers (Address Order) (1/13) Module Register Number of Access Number of Access Reference Address Symbol Register Name Symbol Bits Size States Section 0008 0000h SYSTEM Mode Monitor Register MDMONR 3 ICLK...
Page 93 RX110 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (2/13) Module Register Number of Access Number of Access Reference Address Symbol Register Name Symbol Bits Size States Section 0008 702Dh Interrupt Request Register 045 IR045 2 ICLK section 14.
Page 94 RX110 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (3/13) Module Register Number of Access Number of Access Reference Address Symbol Register Name Symbol Bits Size States Section 0008 70DBh Interrupt Request Register 219 IR219 2 ICLK section 14.
Page 95 RX110 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (4/13) Module Register Number of Access Number of Access Reference Address Symbol Register Name Symbol Bits Size States Section 0008 71F8h DTC Activation Enable Register 248 DTCER248 2 ICLK section 14.
Page 96 RX110 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (5/13) Module Register Number of Access Number of Access Reference Address Symbol Register Name Symbol Bits Size States Section 0008 73DEh Interrupt Source Priority Register 222 IPR222 2 ICLK section 14.
Page 97 RX110 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (6/13) Module Register Number of Access Number of Access Reference Address Symbol Register Name Symbol Bits Size States Section 0008 830Ah RIIC0 Timeout Internal Counter L TMOCNTL 2 or 3 PCLKB section 24.
Page 98 RX110 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (7/13) Module Register Number of Access Number of Access Reference Address Symbol Register Name Symbol Bits Size States Section 0008 8726h MTU0 Timer Buffer Operation Transfer Mode Register TBTM 2 or 3 PCLKB section 19.
Page 99 RX110 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (8/13) Module Register Number of Access Number of Access Reference Address Symbol Register Name Symbol Bits Size States Section 0008 9034h S12AD A/D Data Register 10 ADDR10 2 or 3 PCLKB section 27.
Page 100 RX110 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (9/13) Module Register Number of Access Number of Access Reference Address Symbol Register Name Symbol Bits Size States Section 0008 B082h DOC Data Input Register DODIR 2 or 3 PCLKB section 29.
Page 101 RX110 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (10/13) Module Register Number of Access Number of Access Reference Address Symbol Register Name Symbol Bits Size States Section 0008 C024h PORT4 Port Output Data Register PODR 2 or 3 PCLKB section 18.
Page 102 RX110 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (11/13) Module Register Number of Access Number of Access Reference Address Symbol Register Name Symbol Bits Size States Section 0008 C083h PORT1 Open Drain Control Register 1 ODR1 8, 16 2 or 3 PCLKB...
Page 103 RX110 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (12/13) Module Register Number of Access Number of Access Reference Address Symbol Register Name Symbol Bits Size States Section 0008 C1A4h PC4 Pin Function Control Register PC4PFS 2 or 3 PCLKB section 19.
Page 104 RX110 Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (13/13) Module Register Number of Access Number of Access Reference Address Symbol Register Name Symbol Bits Size States Section 0008 C41Eh Binary Counter 3 Alarm Enable Register BCNT3AER 2 or 3 PCLKB section 21.
Page 105: Resets
RX110 Group 6. Resets Resets Overview There are six types of resets: RES# pin reset, power-on reset, voltage monitoring 1 reset, voltage monitoring 2 reset, independent watchdog timer reset, and software reset. Table 6.1 lists the reset names and sources. Table 6.1 Reset Names and Sources Reset Name...
Page 106 RX110 Group 6. Resets The internal state and pins are initialized by a reset. Table 6.2 lists the reset targets to be initialized. Table 6.2 Targets Initialized According to Reset Source Reset Source Independent Voltage Voltage Power-On Software RES# Pin Reset Watchdog Monitoring 1 Monitoring 2...
Page 107: Register Descriptions
RX110 Group 6. Resets Register Descriptions 6.2.1 Reset Status Register 0 (RSTSR0) Address(es): 0008 C290h LVD2R LVD1R — — — — — PORF Value after reset: Note 1. The value after reset depends on the reset source. Symbol Bit Name Description PORF Power-On Reset Detect Flag...
Page 108: Reset Status Register 1 (Rstsr1)
RX110 Group 6. Resets 6.2.2 Reset Status Register 1 (RSTSR1) Address(es): 0008 C291h — — — — — — — CWSF Value after reset: Note 1. The value after reset depends on the reset source. Symbol Bit Name Description CWSF Cold/Warm Start Determination Flag 0: Cold start R/(W)
Page 109: Reset Status Register 2 (Rstsr2)
RX110 Group 6. Resets 6.2.3 Reset Status Register 2 (RSTSR2) Address(es): 0008 00C0h IWDTR — — — — — SWRF — Value after reset: Note 1. The value after reset depends on the reset source. Symbol Bit Name Description IWDTRF Independent Watchdog Timer Reset Detect 0: Independent watchdog timer reset not detected.
Page 110: Software Reset Register (Swrr)
RX110 Group 6. Resets 6.2.4 Software Reset Register (SWRR) Address(es): 0008 00C2h SWRR[15:0] Value after reset: Symbol Bit Name Description b15 to b0 SWRR[15:0] Software Reset Writing A501h resets the MCU. These bits are read as 0000h. Note: Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register. R01UH0421EJ0120 Rev.1.20 Page 110 of 968 Jul 29, 2016...
Page 111: Operation
RX110 Group 6. Resets Operation 6.3.1 RES# Pin Reset This is a reset generated by the RES# pin. When the RES# pin is driven low, all the processing in progress is aborted and the MCU enters a reset state. To ensure the MCU is reset, the RES# pin should be held low for the specified power supply stabilization time at a power-on.
Page 112 RX110 Group 6. Resets 4.7 k (Reference value) RES# VPOR* External voltage VCC RES# pin Power-on reset state POR signal (low is valid) tPOR Internal reset signal RES# pin reset RSTSR0.PORF Note: For details on the electrical characteristics, refer to section 32, Electrical Characteristics. Note 1.
Page 113: Voltage Monitoring 1 Reset And Voltage Monitoring 2 Reset
RX110 Group 6. Resets 6.3.3 Voltage Monitoring 1 Reset and Voltage Monitoring 2 Reset The voltage monitoring 1 reset and voltage monitoring 2 reset are internal resets generated by the voltage monitoring circuit. When the voltage monitoring 1 interrupt/reset enable bit (LVD1RIE) is set to 1 (enabled) and the voltage monitoring 1 circuit mode select bit (LVD1RI) is set to 1 (voltage monitoring 1 reset enabled when the voltage falls to and below Vdet1) in voltage monitoring 1 circuit control register 0 (LVD1CR0), the RSTSR0.LVD1RF flag is set to 1 and the voltage-detection circuit generates a voltage monitoring 1 reset if VCC falls to or below Vdet1.
Page 114: Independent Watchdog Timer Reset
RX110 Group 6. Resets Vdeti* External voltage RES# pin LVDi valid setting LVCMPCR.LVDiE LVDiCR0.LVDiRN = 0 LVDi reset signal (low is valid) RSTSR0.LVDiRF RES# pin reset tLVDi* Internal reset signal LVDiCR0.LVDiRN = 1 LVDi reset signal (low is valid) RES# pin reset RSTSR0.LVDiRF tLVDi* Internal reset signal...
Page 115: Software Reset
RX110 Group 6. Resets 6.3.5 Software Reset The software reset is an internal reset generated by the software reset circuit. A software reset is generated when A501h is written to the SWRR register. After the software reset has been generated and tRESW2 has elapsed, the internal reset is canceled and the CPU starts the reset exception handling.
Page 116: Determination Of Reset Generation Source
RX110 Group 6. Resets 6.3.7 Determination of Reset Generation Source Reading the RSTSR0 and RSTSR2 registers determines which reset was used to execute the reset exception handling. Figure 6.4 shows an example of the flow to identify a reset generation source. Reset exception handling RSTSR2.
Page 117: Option-Setting Memory
RX110 Group 7. Option-Setting Memory Option-Setting Memory Overview Option-setting memory refers to a set of registers that are provided for selecting the state of the microcontroller after a reset. The option-setting memory is allocated in the ROM. Figure 7.1 shows the option-setting memory area. Addresses Endian select register (MDE) FFFF FF80h to FFFF FF83h...
Page 118: Register Descriptions
RX110 Group 7. Option-Setting Memory Register Descriptions 7.2.1 Option Function Select Register 0 (OFS0) Address(es): FFFF FF8Ch — — — — — — — — — — — — — — — — Value after reset: The value set by the user IWDTS IWDTR IWDTTOPS[1:0] IWDTS...
Page 119 RX110 Group 7. Option-Setting Memory The setting in the OFS0 register is ineffective in boot mode. IWDTSTRT Bit (IWDT Start Mode Select) This bit selects the mode in which the IWDT is activated after a reset (stopped state or activated in auto-start mode). When activated in auto-start mode, the OFS0 register setting for the IWDT is effective.
Page 120: Option Function Select Register 1 (Ofs1)
RX110 Group 7. Option-Setting Memory 7.2.2 Option Function Select Register 1 (OFS1) Address(es): FFFF FF88h — — — — — — — — — — — — — — — — Value after reset: The value set by the user HOCO STUPLV FASTS...
Page 121 RX110 Group 7. Option-Setting Memory FASTSTUP Bit (Power-On Fast Startup Time) The startup time can be reduced by setting this bit to 0 (fast startup time at power on) when it is possible to meet the power-on VCC rising gradient (during fast startup time) shown in Electrical Characteristics. Do not set this bit to 0 when it is not possible to meet the power-on VCC rising gradient (during fast startup time).
Page 122: Endian Select Register (Mde)
RX110 Group 7. Option-Setting Memory 7.2.3 Endian Select Register (MDE) Address(es): FFFF FF80h: MDE (in single-chip mode) — — — — — — — — — — — — — — — — Value after reset: The value set by the user —...
Page 123: Usage Note
RX110 Group 7. Option-Setting Memory Usage Note 7.3.1 Setting Example of Option-Setting Memory Since the option-setting memory is allocated in the ROM, values cannot be written by executing instructions. Write appropriate values when writing the program. An example of the settings is shown below. ...
Page 124: Voltage Detection Circuit (Lvdaa)
RX110 Group 8. Voltage Detection Circuit (LVDAa) Voltage Detection Circuit (LVDAa) The voltage detection circuit (LVD) monitors the voltage level input to the VCC pin using a program. Overview In voltage detection 1, the detection voltage can be selected from 10 levels using the voltage detection level select register (LVDLVLR).
Page 125 RX110 Group 8. Voltage Detection Circuit (LVDAa) Level selection LVD1E circuit (10 levels) LVD1CMPE Voltage detection 1 signal Analog noise filter LVD1LVL[3:0] Internal reference voltage  Vdet1 (for detecting Vdet1) EXVCCINP2 = 0 CMPA2 EXVCCINP2 = 1 Level selection LVD2E circuit (4 levels) LVD2CMPE...
Page 126 RX110 Group 8. Voltage Detection Circuit (LVDAa) Voltage monitoring 2 interrupt/reset circuit Voltage detection 2 circuit The setting of the LVD2DET bit will be 0 EXVCCINP2 = 0 LVD2SR register if 0 (undetected) is written by the program. LVD2LVL[1:0] CMPA2 LVD2E EXVCCINP2 Level...
Page 127: Register Descriptions
RX110 Group 8. Voltage Detection Circuit (LVDAa) Register Descriptions 8.2.1 Voltage Monitoring 1 Circuit Control Register 1 (LVD1CR1) Address(es): 0008 00E0h LVD1IR LVD1IDTSEL — — — — — QSEL [1:0] Value after reset: Symbol Bit Name Description b1, b0 LVD1IDTSEL Voltage Monitoring 1 Interrupt b1 b0 0 0: When VCC ≥...
Page 128: Voltage Monitoring 1 Circuit Status Register (Lvd1Sr)
RX110 Group 8. Voltage Detection Circuit (LVDAa) 8.2.2 Voltage Monitoring 1 Circuit Status Register (LVD1SR) Address(es): 0008 00E1h LVD1M LVD1D — — — — — — Value after reset: Symbol Bit Name Description LVD1DET Voltage Monitoring 1 Voltage Change 0: Not detected R/(W) Detection Flag 1: Vdet1 passage detection...
Page 129: Voltage Monitoring 2 Circuit Control Register 1 (Lvd2Cr1)
RX110 Group 8. Voltage Detection Circuit (LVDAa) 8.2.3 Voltage Monitoring 2 Circuit Control Register 1 (LVD2CR1) Address(es): 0008 00E2h LVD2IR LVD2IDTSEL — — — — — QSEL [1:0] Value after reset: Symbol Bit Name Description b1, b0 LVD2IDTSEL Voltage Monitoring 2 Interrupt b1 b0 0 0: When VCC or the CMPA2 pin ≥...
Page 130: Voltage Monitoring 2 Circuit Status Register (Lvd2Sr)
RX110 Group 8. Voltage Detection Circuit (LVDAa) 8.2.4 Voltage Monitoring 2 Circuit Status Register (LVD2SR) Address(es): 0008 00E3h LVD2M LVD2D — — — — — — Value after reset: Symbol Bit Name Description LVD2DET Voltage Monitoring 2 Voltage Change 0: Not detected R/(W) Detection Flag 1: Vdet2 passage detection...
Page 131: Voltage Monitoring Circuit Control Register (Lvcmpcr)
RX110 Group 8. Voltage Detection Circuit (LVDAa) 8.2.5 Voltage Monitoring Circuit Control Register (LVCMPCR) Address(es): 0008 C297h EXVCC — LVD2E LVD1E — — — — INP2 Value after reset: Note 1. The value after a reset is 1 when the OSF1.STUPLVD1REN bit is 0. Symbol Bit Name Description...
Page 132: Voltage Detection Level Select Register (Lvdlvlr)
RX110 Group 8. Voltage Detection Circuit (LVDAa) 8.2.6 Voltage Detection Level Select Register (LVDLVLR) Address(es): 0008 C298h — — LVD2LVL[1:0] LVD1LVL[3:0] Value after reset: Note 1. The value after a reset is the same as the value of the OFS1.STUPLVD1LVL[3:0] bits when the OSF1.STUPLVD1REN bit is 0.
Page 133: Voltage Monitoring 1 Circuit Control Register 0 (Lvd1Cr0)
RX110 Group 8. Voltage Detection Circuit (LVDAa) 8.2.7 Voltage Monitoring 1 Circuit Control Register 0 (LVD1CR0) Address(es): 0008 C29Ah LVD1R LVD1C LVD1RI LVD1RI — — — — Value after reset: x: Undefined Note 1. The value after a reset is 0 when the OSF1.STUPLVD1REN bit is 0. Note 2.
Page 134: Voltage Monitoring 2 Circuit Control Register 0 (Lvd2Cr0)
RX110 Group 8. Voltage Detection Circuit (LVDAa) 8.2.8 Voltage Monitoring 2 Circuit Control Register 0 (LVD2CR0) Address(es): 0008 C29Bh LVD2R LVD2C LVD2RI LVD2RI — — — — Value after reset: x: Undefined Symbol Bit Name Description LVD2RIE Voltage Monitoring 2 Interrupt/Reset 0: Disabled Enable 1: Enabled...
Page 135: Vcc Input Voltage Monitor
RX110 Group 8. Voltage Detection Circuit (LVDAa) VCC Input Voltage Monitor 8.3.1 Monitoring Vdet1 After making the following settings, the LVD1SR.LVD1MON flag can be used to monitor the results of comparison by voltage monitor 1. (1) Specify the detection voltage by setting the LVDLVLR.LVD1LVL[3:0] bits (voltage detection 1 level select). (2) Set the LVCMPCR.LVD1E bit to 1 (voltage detection 1 circuit enabled).
Page 136: Interrupt And Reset From Voltage Monitoring 1
RX110 Group 8. Voltage Detection Circuit (LVDAa) Interrupt and Reset from Voltage Monitoring 1 Table 8.3 shows the procedures for setting bits related to the voltage monitoring 1 interrupt and voltage monitoring 1 reset. Table 8.4 shows the procedures for stopping bits related to the voltage monitoring 1 interrupt and voltage monitoring 1 reset.
Page 137 RX110 Group 8. Voltage Detection Circuit (LVDAa) Vdet1 Lower limit on VCC voltage (VCCmin) Set to 0 by a program LVD1DET bit LVD1IDTSEL[1:0] bits are set to 10b (when drop and rise are detected) Voltage monitoring 1 interrupt request Set to 0 by a program LVD1DET bit LVD1IDTSEL[1:0] bits are set to 00b (when rise is detected).
Page 138: Interrupt And Reset From Voltage Monitoring 2
RX110 Group 8. Voltage Detection Circuit (LVDAa) Interrupt and Reset from Voltage Monitoring 2 Table 8.5 shows the procedures for setting bits related to the voltage monitoring 2 interrupt and voltage monitoring 2 reset. Table 8.6 shows the procedure for stopping bits related to the voltage monitoring 2 interrupt and voltage monitoring 2 reset.
Page 139 RX110 Group 8. Voltage Detection Circuit (LVDAa) Vdet2 Lower limit on VCC voltage (VCCmin) Set to 0 by a program LVD2DET bit LVD2IDTSEL[1:0] bits are set to 10b (when drop and rise are detected) Voltage monitoring 2 interrupt request Set to 0 by a program LVD2DET bit LVD2IDTSEL[1:0] bits are set to 00b (when rise is detected).
Page 140: Clock Generation Circuit
RX110 Group 9. Clock Generation Circuit Clock Generation Circuit Overview This MCU incorporates a clock generation circuit. Table 9.1 lists the specifications of the clock generation circuit. Figure 9.1 shows a block diagram of the clock generation circuit. Table 9.1 Specifications of Clock Generation Circuit Item Specification...
Page 141 RX110 Group 9. Clock Generation Circuit SCKCR FCK[3:0] FlashIF clock (FCLK) To FlashIF SCKCR ICK[3:0] System clock (ICLK) To CPU, DTC, ROM, and Frequency SCKCR CKSEL[2:0] divider PCKB[3:0], PCKD[3:0] SCKCR3 Peripheral module clock (PCLKB, PCLKD) To peripheral module 1/16 1/32 1/64 XTAL Main clock...
Page 142: Register Descriptions
RX110 Group 9. Clock Generation Circuit Register Descriptions 9.2.1 System Clock Control Register (SCKCR) Address(es): 0008 0020h FCK[3:0] ICK[3:0] — — — — — — — — Value after reset: — — — — PCKB[3:0] — — — — PCKD[3:0] Value after reset: Symbol Bit Name...
Page 143 RX110 Group 9. Clock Generation Circuit 1. Write to the SCKCR register. 2. Confirm that the value has actually been written to the SCKCR register. 3. Proceed to the next step. PCKD[3:0] Bits (Peripheral Module Clock (PCLKD) Select) These bits select the frequency of peripheral module clock D (PCLKD). PCKB[3:0] Bits (Peripheral Module Clock (PCLKB) Select) These bits select the frequency of peripheral module clock B (PCLKB).
Page 144: System Clock Control Register 3 (Sckcr3)
RX110 Group 9. Clock Generation Circuit 9.2.2 System Clock Control Register 3 (SCKCR3) Address(es): 0008 0026h — — — — — CKSEL[2:0] — — — — — — — — Value after reset: Symbol Bit Name Description b7 to b0 —...
Page 145: Main Clock Oscillator Control Register (Mosccr)
RX110 Group 9. Clock Generation Circuit 9.2.3 Main Clock Oscillator Control Register (MOSCCR) Address(es): 0008 0032h — — — — — — — MOSTP Value after reset: Symbol Bit Name Description MOSTP Main Clock Oscillator Stop 0: Main clock oscillator is operating. 1: Main clock oscillator is stopped.
Page 146: Sub-Clock Oscillator Control Register (Sosccr)
RX110 Group 9. Clock Generation Circuit 9.2.4 Sub-Clock Oscillator Control Register (SOSCCR) Address(es): 0008 0033h — — — — — — — SOSTP Value after reset: Symbol Bit Name Description SOSTP Sub-Clock Oscillator Stop 0: Sub-clock oscillator is operating. 1: Sub-clock oscillator is stopped. b7 to b1 —...
Page 147: Low-Speed On-Chip Oscillator Control Register (Lococr)
RX110 Group 9. Clock Generation Circuit 9.2.5 Low-Speed On-Chip Oscillator Control Register (LOCOCR) Address(es): 0008 0034h — — — — — — — LCSTP Value after reset: Symbol Bit Name Description LCSTP LOCO Stop 0: LOCO is operating. 1: LOCO is stopped. b7 to b1 —...
Page 148: Iwdt-Dedicated On-Chip Oscillator Control Register (Ilococr)
RX110 Group 9. Clock Generation Circuit 9.2.6 IWDT-Dedicated On-Chip Oscillator Control Register (ILOCOCR) Address(es): 0008 0035h — — — — — — — ILCSTP Value after reset: Symbol Bit Name Description ILCSTP IWDT-Dedicated On-Chip 0: IWDT-dedicated on-chip oscillator is operating. Oscillator Stop 1: IWDT-dedicated on-chip oscillator is stopped.
Page 149: High-Speed On-Chip Oscillator Control Register (Hococr)
RX110 Group 9. Clock Generation Circuit 9.2.7 High-Speed On-Chip Oscillator Control Register (HOCOCR) Address(es): 0008 0036h — — — — — — — HCSTP Value after reset: Note 1. The HCSTP bit value after a reset is 0 when the HOCO oscillation enable bit in option function select register 1 (OFS1.HOCOEN) is 0.
Page 150: Oscillation Stabilization Flag Register (Oscovfsr)
RX110 Group 9. Clock Generation Circuit 9.2.8 Oscillation Stabilization Flag Register (OSCOVFSR) Address(es): 0008 003Ch MOOV — — — — HCOVF — — Value after reset: 0/1* Note 1. The HCOVF value after a reset is 1 when the HOCO oscillation enable bit in option function selection register 1 (OFS1.HOCOEN) is 0.
Page 151: Oscillation Stop Detection Control Register (Ostdcr)
RX110 Group 9. Clock Generation Circuit 9.2.9 Oscillation Stop Detection Control Register (OSTDCR) Address(es): 0008 0040h OSTDI OSTDE — — — — — — Value after reset: Symbol Bit Name Description OSTDIE Oscillation Stop Detection 0: The oscillation stop detection interrupt is disabled. Interrupt Enable 1: The oscillation stop detection interrupt is enabled.
Page 152: Oscillation Stop Detection Status Register (Ostdsr)
RX110 Group 9. Clock Generation Circuit 9.2.10 Oscillation Stop Detection Status Register (OSTDSR) Address(es): 0008 0041h — — — — — — — OSTDF Value after reset: Symbol Bit Name Description OSTDF Oscillation Stop Detection Flag 0: The main clock oscillation stop has not been detected. R/(W) 1: The main clock oscillation stop has been detected.
Page 153: Main Clock Oscillator Wait Control Register (Moscwtcr)
RX110 Group 9. Clock Generation Circuit 9.2.11 Main Clock Oscillator Wait Control Register (MOSCWTCR) Address(es): 0008 00A2h — — — MSTS[4:0] Value after reset: Symbol Bit Name Description b4 to b0 MSTS[4:0] Main Clock Oscillator Wait Time 0 0 0 0 0: Wait time = 2 cycles (0.5 μs) 0 0 0 0 1: Wait time = 1024 cycles (256 μs) 0 0 0 1 0: Wait time = 2048 cycles (512 μs) 0 0 0 1 1: Wait time = 4096 cycles (1.024 ms)
Page 154: High-Speed On-Chip Oscillator Wait Control Register (Hocowtcr)
RX110 Group 9. Clock Generation Circuit 9.2.12 High-Speed On-Chip Oscillator Wait Control Register (HOCOWTCR) Address(es): 0008 00A5h — — — HSTS[4:0] Value after reset: Symbol Bit Name Description b4 to b0 HSTS[4:0] High-Speed On-Chip Oscillator 0 0 1 0 1: Wait time = 138 cycles (34.5 μs)* Wait Time 0 0 1 1 0: Wait time = 266 cycles (66.5 μs)* Settings other than above are prohibited.
Page 155: Clkout Output Control Register (Ckocr)
RX110 Group 9. Clock Generation Circuit 9.2.13 CLKOUT Output Control Register (CKOCR) Address(es): 0008 003Eh CKOST CKODIV[2:0] — CKOSEL[2:0] — — — — — — — — Value after reset: Symbol Bit Name Description b7 to b0 — Reserved These bits are read as 0. The write value should be 0. b10 to b8 CKOSEL[2:0] CLKOUT Output Source Select...
Page 156: Main Clock Oscillator Forced Oscillation Control Register (Mofcr)
RX110 Group 9. Clock Generation Circuit 9.2.14 Main Clock Oscillator Forced Oscillation Control Register (MOFCR) Address(es): 0008 C293h MOSEL MODR — — — — — — Value after reset: Symbol Bit Name Description b4 to b0 — Reserved These bits are read as 0. The write value should be 0. VCC ≥...
Page 157: Main Clock Oscillator
RX110 Group 9. Clock Generation Circuit Main Clock Oscillator There are two ways of supplying the clock signal from the main clock oscillator: connecting an oscillator or the input of an external clock signal. 9.3.1 Connecting a Crystal Figure 9.2 shows an example of connecting a crystal. A damping resistor (Rd) should be added, if necessary.
Page 158: External Clock Input
RX110 Group 9. Clock Generation Circuit 9.3.2 External Clock Input Figure 9.4 shows connection of an external clock. Set the MOFCR.MOSEL bit to 1 if operation is to be driven by an external clock. In this case, the EXTAL pin will be in the Hi-Z state. EXTAL Hi-Z XTAL...
Page 159: Sub-Clock Oscillator
RX110 Group 9. Clock Generation Circuit Sub-Clock Oscillator The only way of supplying the clock signal from the sub-clock oscillator is connecting a crystal. 9.4.1 Connecting 32.768-kHz Crystal To supply a clock to the sub-clock oscillator, connect a 32.768-kHz crystal, as shown in Figure 9.5 . A damping resistor Rd should be added, if necessary.
Page 160: Oscillation Stop Detection Function
RX110 Group 9. Clock Generation Circuit Oscillation Stop Detection Function 9.5.1 Oscillation Stop Detection and Operation after Detection The oscillation stop detection function is used to detect the main clock oscillator stop and to supply LOCO clock pulses from the low-speed on-chip oscillator as the system clock source instead of the main clock. An oscillation stop detection interrupt request can be generated when an oscillation stop is detected.
Page 161: Oscillation Stop Detection Interrupts
RX110 Group 9. Clock Generation Circuit Start Switch to SCKCR3.CKSEL[2:0] = 000b (LOCO) Setting OSTDCR.OSTDIE = 0 Reading OSTDSR.OSTDF = 1 Setting OSTDSR.OSTDF = 0 OSTDSR.OSTDF = 0 Try again? Switch to SCKCR3.CKSEL[2:0] = 010b (main clock oscillator) Note: On return from the oscillation-stopped state, the factor responsible for stopping the main clock oscillation circuit must be removed on the user system to allow the return of oscillation.
Page 162: Internal Clock
RX110 Group 9. Clock Generation Circuit Internal Clock Clock sources of internal clock signals are the main clock, sub-clock, HOCO clock, LOCO clock, and dedicated low-speed clock for the IWDT. The internal clocks listed below are produced from these sources. (1) Operating clock of the CPU, DTC, ROM, and RAM: System clock (ICLK) (2) Operating clock of peripheral modules: Peripheral module clock (PCLKB and PCLKD) (3) Operating clock of the FlashIF: FlashIF clock (FCLK)
Page 163: Usage Notes
RX110 Group 9. Clock Generation Circuit Usage Notes 9.7.1 Notes on Clock Generation Circuit (1) The frequencies of the system clock (ICLK), peripheral module clocks (PCLKB and PCLKD), and FlashIF clock (FCLK) supplied to each module change according to the settings of the SCKCR register. Each frequency should meet the following: Select each frequency that is within the operation guaranteed range of clock cycle time (tcyc) specified in AC characteristics of electrical characteristics.
Page 164: Notes On Sub-Clock
RX110 Group 9. Clock Generation Circuit 9.7.4 Notes on Sub-Clock The sub-clock can be used as the system clock, as the count source for the realtime clock, or as both. Take note of the following limitations and points for caution regarding the settings, including when the sub-clock is not in use. ...
Page 165 RX110 Group 9. Clock Generation Circuit  When using the sub-clock only as the count source of the realtime clock, perform initial settings according to the flowchart example shown in Figure 9.10 . After that, perform the clock setting procedure shown in section 21.3.2, Clock and Count Mode Setting Procedure .
Page 166 RX110 Group 9. Clock Generation Circuit  When using the sub-clock only as the system clock, perform initial settings according to the flowchart example shown in Figure 9.11 . Sub-clock SOSCCR. RCR3. Start oscillation state SOSTP RTCEN Set the SOSCCR.SOSTP bit to 1 (sub-clock oscillator is stopped). Oscillating Undefined Read the SOSCCR.SOSTP bit and confirm that it is 1.
Page 167 RX110 Group 9. Clock Generation Circuit  When not using the sub-clock, perform initial settings according to the flowchart example in Figure 9.12 . Sub-clock SOSCCR. RCR3. Start oscillation state SOSTP RTCEN Set the SOSCCR.SOSTP bit to 1 (sub-clock oscillator is stopped). Undefined Read the SOSCCR.SOSTP bit and confirm that it is 1.
Page 168: Clock Frequency Accuracy Measurement Circuit (Cac)
RX110 Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) Clock Frequency Accuracy Measurement Circuit (CAC) 10.1 Overview The clock frequency accuracy measurement circuit (CAC) counts pulses of the clock to be measured (measurement target clock) within the time generated by the clock to be used as a measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range.
Page 169 RX110 Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) DFS[1:0] CACREFE DFS[1:0] CACREF pin Digital filter RSCS[2:0] RCDS[1:0] EDGES[1:0] 1/32 Reference 1/128 Edge detection signal circuit generation 1/1024 clock select 1/8192 circuit Valid edge signal FMCS[2:0] TCSS[1:0] Frequency measurement clock Main clock CFME Sub-clock...
Page 170: Register Descriptions
RX110 Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2 Register Descriptions 10.2.1 CAC Control Register 0 (CACR0) Address(es): 0008 B000h — — — — — — — CFME Value after reset: Symbol Bit Name Description CFME Clock Frequency Measurement Enable 0: Clock frequency measurement is disabled.
Page 171: Cac Control Register 1 (Cacr1)
RX110 Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.2 CAC Control Register 1 (CACR1) Address(es): 0008 B001h CACRE EDGES[1:0] TCSS[1:0] FMCS[2:0] Value after reset: Symbol Bit Name Description CACREFE CACREF Pin Input Enable 0: CACREF pin input is disabled. 1: CACREF pin input is enabled.
Page 172: Cac Control Register 2 (Cacr2)
RX110 Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.3 CAC Control Register 2 (CACR2) Address(es): 0008 B002h DFS[1:0] RCDS[1:0] RSCS[2:0] Value after reset: Symbol Bit Name Description Reference Signal Select 0: CACREF pin input 1: Internal clock (internally generated signal) b3 to b1 RSCS[2:0] Measurement Reference Clock...
Page 173: Cac Interrupt Request Enable Register (Caicr)
RX110 Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.4 CAC Interrupt Request Enable Register (CAICR) Address(es): 0008 B003h OVFFC MENDF FERRF OVFIE MENDI FERRI — — Value after reset: Symbol Bit Name Description FERRIE Frequency Error Interrupt Request 0: Frequency error interrupt request is disabled. Enable 1: Frequency error interrupt request is enabled.
Page 174: Cac Status Register (Castr)
RX110 Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.5 CAC Status Register (CASTR) Address(es): 0008 B004h — — — — — OVFF MENDF FERRF Value after reset: Symbol Bit Name Description FERRF Frequency Error Flag 0: The clock frequency is within the range corresponding to the settings.
Page 175: Cac Upper-Limit Value Setting Register (Caulvr)
RX110 Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.6 CAC Upper-Limit Value Setting Register (CAULVR) Address(es): 0008 B006h Value after reset: CAULVR is a 16-bit readable/writable register that specifies the upper-limit value of the counter used for measuring the frequency.
Page 176: Operation
RX110 Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.3 Operation 10.3.1 Measuring Clock Frequency The clock frequency accuracy measurement circuit measures the clock frequency using the CACREF pin input or the internal clock as a reference. Figure 10.2 shows an operating example of the clock frequency accuracy measurement circuit.
Page 177: Digital Filtering Of Signals On The Cacref Pin
RX110 Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) clock frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt is generated. Also, the MENDF flag in CASTR is set to 1. If the MENDIE bit in CAICR is 1, a measurement end interrupt is generated. (5) When the next valid edge is input, the counter value is transferred in CACNTBR and compared with the values of CAULVR and CALLVR.
Page 178: Usage Notes
RX110 Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.5 Usage Notes 10.5.1 Module Stop Function Setting CAC operation can be disabled or enabled using module stop control register C (MSTPCRC). The initial setting is for the CAC to be halted. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 179: Low Power Consumption
RX110 Group 11. Low Power Consumption Low Power Consumption 11.1 Overview This MCU has several functions for reducing power consumption, by setting clock dividers, stopping modules, changing to low power consumption mode in normal operation, and changing to operating power control mode. Table 11.1 lists the specifications of low power consumption functions, and Table 11.2 lists the conditions to change to low power consumption modes, states of the CPU and peripheral modules, and the method for exiting each mode.
Page 180 RX110 Group 11. Low Power Consumption Table 11.2 Operating Conditions of Each Power Consumption Mode Sleep Mode Deep Sleep Mode Software Standby Mode Entry trigger Control register + instruction Control register + instruction Control register + instruction Exit trigger Interrupt Interrupt Interrupt* After exiting from each mode, CPU...
Page 181 RX110 Group 11. Low Power Consumption Reset state Normal operation mode (Program execution state) WAIT instruction* WAIT instruction* WAIT instruction* SSBY = 0 All interrupts Interrupt* All interrupts MSTPCRA.MSTPA28 = 1 SSBY = 1 SSBY = 0 MSTPCRC.DSLPE = 1 Software standby Sleep mode Deep sleep mode...
Page 182 RX110 Group 11. Low Power Consumption Reset state Software Software Deep sleep mode Deep sleep mode standby mode standby mode Exit the reset state High-speed Middle-speed Sleep mode Sleep mode operating mode operating mode Set the OPCCR register the SOPCCR the SOPCCR register register...
Page 183: Register Descriptions
RX110 Group 11. Low Power Consumption 11.2 Register Descriptions 11.2.1 Standby Control Register (SBYCR) Address(es): 0008 000Ch SSBY — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description b14 to b0 —...
Page 184: Module Stop Control Register A (Mstpcra)
RX110 Group 11. Low Power Consumption 11.2.2 Module Stop Control Register A (MSTPCRA) Address(es): 0008 0010h MSTPA MSTPA — — — — — — — — — — — — — — Value after reset: MSTPA MSTPA — — — —...
Page 185: Module Stop Control Register B (Mstpcrb)
RX110 Group 11. Low Power Consumption 11.2.3 Module Stop Control Register B (MSTPCRB) Address(es): 0008 0014h MSTPB MSTPB MSTPB MSTPB MSTPB — — — — — — — — — — — Value after reset: MSTPB MSTPB — — — —...
Page 186: Module Stop Control Register C (Mstpcrc)
RX110 Group 11. Low Power Consumption 11.2.4 Module Stop Control Register C (MSTPCRC) Address(es): 0008 0018h MSTPC DSLPE — — — — — — — — — — — — — — Value after reset: MSTPC — — — — —...
Page 187: Operating Power Control Register (Opccr)
RX110 Group 11. Low Power Consumption 11.2.5 Operating Power Control Register (OPCCR) Address(es): 0008 00A0h OPCM — — — — OPCM[2:0] Value after reset: Symbol Bit Name Description b2 to b0 OPCM[2:0] Operating Power Control 0 0 0: High-speed operating mode Mode Select 0 1 0: Middle-speed operating mode Settings other than above are prohibited.
Page 188: Sub Operating Power Control Register (Sopccr)
RX110 Group 11. Low Power Consumption 11.2.6 Sub Operating Power Control Register (SOPCCR) Address(es): 0008 00AAh SOPC SOPC — — — — — — MTSF Value after reset: Symbol Bit Name Description SOPCM Sub Operating Power Control 0: High-speed operating mode or middle-speed operating mode* Mode Select 1: Low-speed operating mode b3 to b1...
Page 189 RX110 Group 11. Low Power Consumption SOPCMTSF Flag (Sub Operating Power Control Mode Transition Status Flag) The SOPCMTSF flag indicates the switching control state when the sub operating power control mode is switched. This flag becomes 1 when the value of the SOPCM bit is rewritten, and 0 when mode transition is completed. Read this flag and confirm that it is 0 before proceeding to the next processing.
Page 190 RX110 Group 11. Low Power Consumption  High-Speed Operating Mode The maximum operating frequency during FLASH read is 32 MHz for ICLK, FCLK, PCLKD, and PCLKB. The operating voltage range is 1.8 to 3.6 V during FLASH read. However, for ICLK, FCLK, PCLKD, and PCLKB, the maximum operating frequency during FLASH read is 16 MHz when the operating voltage is 2.4 V or larger and smaller than 2.7 V.
Page 191 RX110 Group 11. Low Power Consumption  Middle-Speed Operating Mode As compared to high-speed operating mode, this mode reduces power consumption for low-speed operation. The maximum operating frequency during FLASH read is 12 MHz for ICLK, FCLK, PCLKD, and PCLKB. The operating voltage range is 1.8 to 3.6 V during FLASH read.
Page 192 RX110 Group 11. Low Power Consumption  Low-Speed Operating Mode A transition to low-speed operating mode is set by writing 1 to the SOPCM bit in the SOPCCR register. The setting of the OPCM[2:0] bits cannot be modified during low-speed operating mode. This mode is used only for the sub oscillator of 32.768 kHz.
Page 193: Sleep Mode Return Clock Source Switching Register (Rstckcr)
RX110 Group 11. Low Power Consumption 11.2.7 Sleep Mode Return Clock Source Switching Register (RSTCKCR) Address(es): 0008 00A1h RSTCK — — — — RSTCKSEL[2:0] Value after reset: Symbol Bit Name Description b2 to b0 RSTCKSEL Sleep Mode Return Clock 0 0 0: LOCO is selected [2:0] Source Select 0 0 1: HOCO is selected*...
Page 194 RX110 Group 11. Low Power Consumption RSTCKEN Bit (Sleep Mode Return Clock Source Switching Enable) The RSTCKEN bit enables or disables clock source switching when sleep mode is exited. When returning from sleep mode while this bit is enabled, the SOPCM bit in the SOPCCR register is automatically rewritten to 0 (middle-speed operating mode or high-speed operating mode).
Page 195: Reducing Power Consumption By Switching Clock Signals
RX110 Group 11. Low Power Consumption 11.3 Reducing Power Consumption by Switching Clock Signals The clock frequency can change by setting the SCKCR.FCK[3:0], ICK[3:0], PCKB[3:0], and PCKD[3:0] bits. The CPU, DTC, ROM, and RAM clocks can be set by the ICK[3:0] bits. The peripheral module clocks can be set by the PCKB[3:0] and PCKD[3:0] bits.
Page 196 RX110 Group 11. Low Power Consumption  Example 2: From high-speed/middle-speed operating mode to low-speed operating mode (High-speed operation in high-speed operating mode/middle-speed operation in middle-speed operating mode) ↓ Set the frequency of each clock to lower than the maximum operating frequency for low-speed operating mode ↓...
Page 197: Low Power Consumption Modes
RX110 Group 11. Low Power Consumption 11.6 Low Power Consumption Modes 11.6.1 Sleep Mode 11.6.1.1 Entry to Sleep Mode When the WAIT instruction is executed while the SBYCR.SSBY bit is 0, the CPU enters sleep mode. In sleep mode, the CPU stops operating but the contents of its internal registers are retained.
Page 198: Exit From Sleep Mode
RX110 Group 11. Low Power Consumption 11.6.1.2 Exit from Sleep Mode Exit from sleep mode is initiated by any interrupt, a RES# pin reset, a power-on reset, a voltage monitoring reset, or a reset caused by an IWDT underflow.  Initiated by an interrupt An interrupt initiates exit from sleep mode and the interrupt exception handling starts.
Page 199: Deep Sleep Mode
RX110 Group 11. Low Power Consumption 11.6.2 Deep Sleep Mode 11.6.2.1 Entry to Deep Sleep Mode When a WAIT instruction is executed with the MSTPCRC.DSLPE bit set to 1, the MSTPCRA.MSTPA28 bit set to 1, and the SBYCR.SSBY bit cleared to 0, a transition to deep sleep mode is made. In deep sleep mode, the CPU and the DTC, ROM, and RAM clocks stop.
Page 200: Exit From Deep Sleep Mode
RX110 Group 11. Low Power Consumption 11.6.2.2 Exit from Deep Sleep Mode Exit from deep sleep mode is initiated by any interrupt, a RES# pin reset, a power-on reset, a voltage monitoring reset, or a reset caused by an IWDT underflow. ...
Page 201: Software Standby Mode
RX110 Group 11. Low Power Consumption 11.6.3 Software Standby Mode 11.6.3.1 Entry to Software Standby Mode When a WAIT instruction is executed with the SBYCR.SSBY bit set to 1, a transition to software standby mode is made. In this mode, the CPU, on-chip peripheral functions, and all the other functions except the sub-clock oscillator stop. However, the contents of the CPU internal registers, RAM data, the states of on-chip peripheral functions, the I/O ports, and the sub-clock oscillator are retained.
Page 202: Exit From Software Standby Mode
RX110 Group 11. Low Power Consumption 11.6.3.2 Exit from Software Standby Mode Exit from software standby mode is initiated by an external pin interrupt (the NMI or IRQ0 to IRQ7), peripheral interrupts (the RTC alarm, RTC interval, IWDT, and voltage monitoring interrupts), a RES# pin reset, a power-on reset, a voltage monitoring reset, or an independent watchdog timer reset.
Page 203: Example Of Software Standby Mode Application
RX110 Group 11. Low Power Consumption 11.6.3.3 Example of Software Standby Mode Application Figure 11.6 shows an example of entry to software standby mode by the falling edge of the IRQn pin, and exit from software standby mode by the rising edge of the IRQn pin. In this example, an IRQn interrupt is accepted with the IRQCRi.IRQMD[1:0] bits of the ICU set to 01b (falling edge), and then the IRQCRi.IRQMD[1:0] bits are set to 10b (rising edge).
Page 204: Usage Notes
RX110 Group 11. Low Power Consumption 11.7 Usage Notes 11.7.1 I/O Port States I/O port states are retained in software standby mode. Therefore, the supply current is not reduced if output signals are high level. 11.7.2 Module Stop State of DTC Before setting the MSTPCRA.MSTPA28 bit to 1, set the DTCST.DTCST bit of the DTC to 0 to avoid activating the DTC module.
Page 205: Register Write Protection Function
RX110 Group 12. Register Write Protection Function Register Write Protection Function The register write protection function protects important registers from being overwritten for in case a program runs out of control. The registers to be protected are set with the protect register (PRCR). Table 12.1 lists the association between the PRCR bits and the registers to be protected.
Page 206: Register Descriptions
RX110 Group 12. Register Write Protection Function 12.1 Register Descriptions 12.1.1 Protect Register (PRCR) Address(es): 0008 03FEh PRKEY[7:0] — — — — PRC3 PRC2 PRC1 PRC0 Value after reset: Symbol Bit Name Function PRC0 Protect Bit 0 Enables writing to the registers related to the clock generation circuit. 0: Write disabled 1: Write enabled PRC1...
Page 207: Exception Handling
RX110 Group 13. Exception Handling Exception Handling 13.1 Exception Events During execution of a program by the CPU, the occurrence of a certain event may cause execution of that program to be suspended and execution of another program to be started. Such kinds of events are called exception events. The RX CPU supports six types of exceptions.
Page 208: Undefined Instruction Exception
RX110 Group 13. Exception Handling 13.1.1 Undefined Instruction Exception An undefined instruction exception occurs when execution of an undefined instruction (an instruction not implemented) is detected. 13.1.2 Privileged Instruction Exception A privileged instruction exception occurs when execution of a privileged instruction is detected in user mode. Privileged instructions can be executed only in supervisor mode.
Page 209: Exception Handling Procedure
RX110 Group 13. Exception Handling 13.2 Exception Handling Procedure In the exception handling, part of the processing is handled automatically by hardware and part of it is handled by a program (exception handling routine) that has been written by the user. Figure 13.2 shows the processing procedure when an exception other than a reset is accepted.
Page 210 RX110 Group 13. Exception Handling When an exception is accepted, hardware processing by the RX CPU is followed by access to the vector to acquire the address of the branch destination. In the vector, a vector address is allocated to each exception, and the branch destination address of the exception handling routine is written to each vector address.
Page 211: Acceptance Of Exception Events
RX110 Group 13. Exception Handling 13.3 Acceptance of Exception Events When an exception occurs, the CPU suspends the execution of the program and processing branches to the exception handling routine. 13.3.1 Acceptance Timing and Saved PC Value Table 13.1 lists the timing of acceptance and the program counter (PC) value to be saved for each exception event. Table 13.1 Acceptance Timing and Saved PC Value Acceptance...
Page 212: Hardware Processing For Accepting And Returning From Exceptions
RX110 Group 13. Exception Handling 13.4 Hardware Processing for Accepting and Returning from Exceptions This section describes the hardware processing for accepting and returning from exceptions other than a reset. (1) Hardware Pre-Processing for Accepting an Exception (a) Saving PSW ...
Page 213: Hardware Pre-Processing
RX110 Group 13. Exception Handling 13.5 Hardware Pre-Processing The hardware pre-processing from reception of each exception request to execution of the associated exception handling routine are explained below. 13.5.1 Undefined Instruction Exception 1. The value of the processor status word (PSW) is saved on the stack (ISP). 2.
Page 214: Interrupt
RX110 Group 13. Exception Handling 13.5.5 Interrupt 1. The value of the processor status word (PSW) is saved on the stack (ISP) or, for the fast interrupt, in the backup PSW (BPSW). 2. The processor mode select bit (PM), the stack pointer select bit (U), and the interrupt enable bit (I) in PSW are set to 3.
Page 215: Return From Exception Handling Routine
RX110 Group 13. Exception Handling 13.6 Return from Exception Handling Routine Executing the instruction listed in Table 13.3 at the end of the corresponding exception handling routine restores the values of the program counter (PC) and processor status word (PSW) that were saved on the stack or in the control registers (BPC and BPSW) immediately before the exception handling sequence.
Page 216: Interrupt Controller (Icub)
RX110 Group 14. Interrupt Controller (ICUb) Interrupt Controller (ICUb) In this section, “PCLK” is used to refer to PCLKB. 14.1 Overview The interrupt controller receives interrupt signals from peripheral modules and external pins, sends interrupts to the CPU, and activates the DTC. Table 14.1 lists the specifications of the interrupt controller, and Figure 14.1 shows a block diagram of the interrupt controller.
Page 217 RX110 Group 14. Interrupt Controller (ICUb) Interrupt controller Voltage monitoring 2 interrupt Clock Voltage monitoring 1 interrupt generation Clock restoration request IWDT underflow/refresh error circuit Clock Oscillation stop detection interrupt restoration NMI pin Digital filter Detection judgment Clock restoration enable level Non-maskable interrupt request IFLTE IFLTC...
Page 218: Register Descriptions
RX110 Group 14. Interrupt Controller (ICUb) 14.2 Register Descriptions 14.2.1 Interrupt Request Register n (IRn) (n = interrupt vector number) Address(es): 0008 7010h to 0008 70F9h — — — — — — — Value after reset: Symbol Bit Name Description Interrupt Status Flag 0: Interrupt not requested R/(W)
Page 219: Interrupt Request Enable Register M (Ierm) (M = 02H To 1Fh)
RX110 Group 14. Interrupt Controller (ICUb) 14.2.2 Interrupt Request Enable Register m (IERm) (m = 02h to 1Fh) Address(es): 0008 7202h to 0008 721Fh IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 Value after reset: Symbol Bit Name Description IEN0 Interrupt Request Enable 0 0: Interrupt request is disabled 1: Interrupt request is enabled...
Page 220: Interrupt Source Priority Register N (Iprn) (N = 000 To 249)
RX110 Group 14. Interrupt Controller (ICUb) 14.2.3 Interrupt Source Priority Register n (IPRn) (n = 000 to 249) Address(es): 0008 7300h to 0008 73F9h — — — — IPR[3:0] Value after reset: Symbol Bit Name Description b3 to b0 IPR[3:0] Interrupt Priority Level Select 0 0 0 0: Level 0 (interrupt disabled)* 0 0 0 1: Level 1...
Page 221: Fast Interrupt Set Register (Fir)
RX110 Group 14. Interrupt Controller (ICUb) 14.2.4 Fast Interrupt Set Register (FIR) Address(es): 0008 72F0h FIEN — — — — — — — FVCT[7:0] Value after reset: Symbol Bit Name Description b7 to b0 FVCT[7:0] Fast Interrupt Vector Number Specify the vector number of an interrupt source to be a fast interrupt.
Page 222: Software Interrupt Activation Register (Swintr)
RX110 Group 14. Interrupt Controller (ICUb) 14.2.5 Software Interrupt Activation Register (SWINTR) Address(es): 0008 72E0h — — — — — — — SWINT Value after reset: Symbol Bit Name Description SWINT Software Interrupt Activation This bit is read as 0. Writing 1 issues a software interrupt request. R/(W) Writing 0 to this bit has no effect.
Page 223: Dtc Activation Enable Register N (Dtcern) (N = Interrupt Vector Number)
RX110 Group 14. Interrupt Controller (ICUb) 14.2.6 DTC Activation Enable Register n (DTCERn) (n = interrupt vector number) Address(es): 0008 711Bh to 0008 71F8h — — — — — — — DTCE Value after reset: Symbol Bit Name Description DTCE DTC Activation Enable 0: DTC activation is disabled 1: DTC activation is enabled...
Page 224: Irq Control Register I (Irqcri) (I = 0 To 7)
RX110 Group 14. Interrupt Controller (ICUb) 14.2.7 IRQ Control Register i (IRQCRi) (i = 0 to 7) Address(es): 0008 7500h to 0008 7507h — — — — IRQMD[1:0] — — Value after reset: Symbol Bit Name Description b1, b0 — Reserved These bits are read as 0.
Page 225: Irq Pin Digital Filter Enable Register 0 (Irqflte0)
RX110 Group 14. Interrupt Controller (ICUb) 14.2.8 IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0) Address(es): 0008 7510h FLTEN FLTEN FLTEN FLTEN FLTEN FLTEN FLTEN FLTEN Value after reset: Symbol Bit Name Description FLTEN0 IRQ0 Digital Filter Enable 0: Digital filter disabled 1: Digital filter enabled FLTEN1 IRQ1 Digital Filter Enable...
Page 226: Irq Pin Digital Filter Setting Register 0 (Irqfltc0)
RX110 Group 14. Interrupt Controller (ICUb) 14.2.9 IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0) Address(es): 0008 7514h FCLKSEL7[1:0] FCLKSEL6[1:0] FCLKSEL5[1:0] FCLKSEL4[1:0] FCLKSEL3[1:0] FCLKSEL2[1:0] FCLKSEL1[1:0] FCLKSEL0[1:0] Value after reset: Symbol Bit Name Description b1, b0 FCLKSEL0[1:0] IRQ0 Digital Filter Sampling Clock 0 0: PCLK 0 1: PCLK/8 b3, b2...
Page 227: Non-Maskable Interrupt Status Register (Nmisr)
RX110 Group 14. Interrupt Controller (ICUb) 14.2.10 Non-Maskable Interrupt Status Register (NMISR) Address(es): 0008 7580h LVD2S LVD1S IWDTS — — — OSTST NMIST Value after reset: Symbol Bit Name Description NMIST NMI Status Flag 0: NMI pin interrupt is not requested 1: NMI pin interrupt is requested OSTST Oscillation Stop Detection...
Page 228 RX110 Group 14. Interrupt Controller (ICUb) IWDTST Flag (IWDT Underflow/Refresh Error Status Flag) This flag indicates the IWDT underflow/refresh error interrupt request. The IWDTST flag is read-only, and cleared by the NMICLR.IWDTCLR bit. [Setting condition]  When the IWDT underflow/refresh error interrupt is generated while this interrupt is enabled at its source. [Clearing condition] ...
Page 229: Non-Maskable Interrupt Enable Register (Nmier)
RX110 Group 14. Interrupt Controller (ICUb) 14.2.11 Non-Maskable Interrupt Enable Register (NMIER) Address(es): 0008 7581h LVD2E LVD1E IWDTE — — — OSTEN NMIEN Value after reset: Symbol Bit Name Description NMIEN NMI Pin Interrupt Enable 0: NMI pin interrupt is disabled R/(W) 1: NMI pin interrupt is enabled OSTEN...
Page 230: Non-Maskable Interrupt Status Clear Register (Nmiclr)
RX110 Group 14. Interrupt Controller (ICUb) 14.2.12 Non-Maskable Interrupt Status Clear Register (NMICLR) Address(es): 0008 7582h LVD2C LVD1C IWDTC OSTCL NMICL — — — Value after reset: Symbol Bit Name Description NMICLR NMI Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.NMIST flag. R/(W) Writing 0 to this bit has no effect.
Page 231: Nmi Pin Interrupt Control Register (Nmicr)
RX110 Group 14. Interrupt Controller (ICUb) 14.2.13 NMI Pin Interrupt Control Register (NMICR) Address(es): 0008 7583h — — — — NMIMD — — — Value after reset: Symbol Bit Name Description b2 to b0 — Reserved These bits are read as 0. The write value should be 0. NMIMD NMI Detection Set 0: Falling edge...
Page 232: Nmi Pin Digital Filter Setting Register (Nmifltc)
RX110 Group 14. Interrupt Controller (ICUb) 14.2.15 NMI Pin Digital Filter Setting Register (NMIFLTC) Address(es): 0008 7594h — — — — — — NFCLKSEL[1:0] Value after reset: Symbol Bit Name Description b1, b0 NFCLKSEL[1:0] NMI Digital Filter Sampling b1 b0 0 0: PCLK Clock 0 1: PCLK/8...
Page 233: Vector Table
RX110 Group 14. Interrupt Controller (ICUb) 14.3 Vector Table There are two types of interrupts detected by the interrupt controller: maskable interrupts and non-maskable interrupts. When the CPU accepts an interrupt or non-maskable interrupt, it acquires a 4-byte vector address from the vector table. 14.3.1 Interrupt Vector Table The interrupt vector table is placed in the 1024-byte range (4 bytes ×...
Page 234 RX110 Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (1/7) Source of Interrupt Vector Form of Request Vector Address Interrupt sstb Generation Name No.* Offset Detection Return DTCER — For an 0000h — × × × — — —...
Page 235 RX110 Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (2/7) Source of Interrupt Vector Form of Request Vector Address Interrupt sstb Generation Name No.* Offset Detection Return DTCER — Reserved 0054h — × × × — — — —...
Page 236 RX110 Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (3/7) Source of Interrupt Vector Form of Request Vector Address Interrupt sstb Generation Name No.* Offset Detection Return DTCER ○ ○ ○ IRQ0 0100h Edge/Level IER08.IEN0 IPR064 DTCER064 ○ ○...
Page 237 RX110 Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (4/7) Source of Interrupt Vector Form of Request Vector Address Interrupt sstb Generation Name No.* Offset Detection Return DTCER — Reserved 01ACh — × × × — — — —...
Page 238 RX110 Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (5/7) Source of Interrupt Vector Form of Request Vector Address Interrupt sstb Generation Name No.* Offset Detection Return DTCER — Reserved 0258h — × × × — — — —...
Page 239 RX110 Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (6/7) Source of Interrupt Vector Form of Request Vector Address Interrupt sstb Generation Name No.* Offset Detection Return DTCER — Reserved 0304h — × × × — — — —...
Page 240 RX110 Group 14. Interrupt Controller (ICUb) Table 14.3 Interrupt Vector Table (7/7) Source of Interrupt Vector Form of Request Vector Address Interrupt sstb Generation Name No.* Offset Detection Return DTCER — Reserved 03B0h — × × × — — — —...
Page 241: Fast Interrupt Vector Table
RX110 Group 14. Interrupt Controller (ICUb) 14.3.2 Fast Interrupt Vector Table The address of the entry in the interrupt vector table that corresponds to the vector number of the fast interrupt is placed in the fast interrupt vector register (FINTV) of the CPU. 14.3.3 Non-maskable Interrupt Vector Table The non-maskable interrupt vector table area is FFFF FFF8h.
Page 242 RX110 Group 14. Interrupt Controller (ICUb) Figure 14.3 to Figure 14.5 show the interrupt signals of the interrupt controller. Note that the timings of the interrupts with interrupt vector numbers 64 to 95 are different from those of other interrupts. For the IRQ pin interrupts with interrupt vector numbers 64 to 79, “internal delay + 2 PCLK cycles”...
Page 243: Operation Of Status Flags For Level-Detected Interrupts
RX110 Group 14. Interrupt Controller (ICUb) 14.4.1.2 Operation of Status Flags for Level-Detected Interrupts Figure 14.5 shows the operation of the interrupt status flag (IR flag) in IRn in the case of level detection of an interrupt from a peripheral module or an external pin. The IRn.IR flag remains set to 1 as long as the interrupt signal is asserted.
Page 244: Enabling And Disabling Interrupt Sources
RX110 Group 14. Interrupt Controller (ICUb) 14.4.2 Enabling and Disabling Interrupt Sources Enabling requests from a given interrupt source requires the following settings. 1. In the case of interrupt requests from peripheral modules, setting the interrupt enable bit for the peripheral module to permit the output of interrupt requests from the source 2.
Page 245: Determining Priority
RX110 Group 14. Interrupt Controller (ICUb) Table 14.4 Operation at DTC Activation Interrupt Request Remaining Number of Operation for Interrupt Request Destination after Destination DISEL Transfer Operations Each Request Transfer ≠ 0 DTC* DTC transfer Cleared on interrupt acceptance by →...
Page 246: Fast Interrupt
RX110 Group 14. Interrupt Controller (ICUb) 14.4.6 Fast Interrupt The fast interrupt is an interrupt for executing a faster interrupt response by the CPU, so only one of the interrupt sources can be assigned. The interrupt priority level of the fast interrupt is 15 (highest) regardless of the setting of the IPRn.IPR[3:0] bits. In addition, the fast interrupt is accepted with precedence over other interrupt sources with level 15.
Page 247: External Pin Interrupts
RX110 Group 14. Interrupt Controller (ICUb) 14.4.8 External Pin Interrupts The procedure for using the signal on an external pin as an interrupt is as follows. 1. Set the IERm.IENj bit to 0 (interrupt request disabled). 2. Set the IRQFLTE0.FLTENi bit (i = 0 to 7) to 0 (digital filter disabled). 3.
Page 248: Non-Maskable Interrupt Operation
RX110 Group 14. Interrupt Controller (ICUb) 14.5 Non-maskable Interrupt Operation There are six types of non-maskable interrupt: the NMI pin interrupt, oscillation stop detection interrupt, IWDT underflow/refresh error, voltage monitoring 1 interrupt, and voltage monitoring 2 interrupt. Non-maskable interrupts are only usable as interrupts for the CPU;...
Page 249: Return From Power-Down States
RX110 Group 14. Interrupt Controller (ICUb) 14.6 Return from Power-Down States The interrupt sources that can be used to return operation from sleep mode, deep sleep mode, or software standby mode are listed in Table 14.3, Interrupt Vector Table . For details, refer to section 11, Low Power Consumption .
Page 250: Buses
RX110 Group 15. Buses Buses 15.1 Overview Table 15.1 lists the bus specifications, Figure 15.1 shows the bus configuration, and Table 15.2 lists the addresses assigned to each bus. Table 15.1 Bus Specifications Bus Type Description  Connected to the CPU for instructions CPU bus Instruction bus ...
Page 251 RX110 Group 15. Buses ICLK synchronization Instruction bus Operand bus Memory Memory Bus error bus 1 bus 2 monitoring section DTC (m) Internal main bus 1 Internal main bus 2 Internal Internal peripheral peripheral bus 1 Internal bus 2 peripheral bus 6 Peripheral DTC (s) Peripheral...
Page 252: Description Of Buses
RX110 Group 15. Buses 15.2 Description of Buses 15.2.1 CPU Buses The CPU buses consist of the instruction and operand buses, which are connected to internal main bus 1. As the names suggest, the instruction bus is used to fetch instructions for the CPU, while the operand bus is used for operand access. Connection of the instruction and operand buses to RAM and ROM provides the CPU with direct access to these areas, i.e.
Page 253: Internal Peripheral Buses
RX110 Group 15. Buses 15.2.4 Internal Peripheral Buses Connection of peripheral modules to the internal peripheral buses is as described in Table 15.4 . Table 15.4 Connection of Peripheral Modules to the Internal Peripheral Buses Type of Bus Peripheral Modules Internal peripheral bus 1 DTC, interrupt controller, and bus error monitoring section Internal peripheral bus 2...
Page 254: Write Buffer Function (Internal Peripheral Bus)
RX110 Group 15. Buses 15.2.5 Write Buffer Function (Internal Peripheral Bus) The internal peripheral bus has the write buffer function, which allows the next round of bus access to start, before the current write access is completed, in write access. However, if the following round of bus access is from the same bus master but to the different internal peripheral bus, it is suspended until the bus operations already in progress are completed.
Page 255: Parallel Operation
RX110 Group 15. Buses 15.2.6 Parallel Operation Parallel operation is possible when different bus-master modules are requesting access to different slave modules. For example, if the CPU is fetching an instruction from ROM and an operand from RAM, the DTC is able to handle transfer between a peripheral bus and peripheral bus at the same time.
Page 256: Register Descriptions
RX110 Group 15. Buses 15.3 Register Descriptions 15.3.1 Bus Error Status Clear Register (BERCLR) Address(es): 0008 1300h STSCL — — — — — — — Value after reset: Symbol Bit Name Description STSCLR Status Clear 0: Invalid (W)* 1: Bus error status register cleared b7 to b1 —...
Page 257: Bus Error Status Register 1 (Bersr1)
RX110 Group 15. Buses 15.3.3 Bus Error Status Register 1 (BERSR1) Address(es): 0008 1308h — MST[2:0] — — Value after reset: Symbol Bit Name Description Illegal Address Access 0: Illegal address access not made 1: Illegal address access made Timeout 0: Timeout not generated 1: Timeout generated b3, b2...
Page 258: Bus Priority Control Register (Buspri)
RX110 Group 15. Buses 15.3.5 Bus Priority Control Register (BUSPRI) Address(es): 0008 1310h — — — — BPFB[1:0] — — BPGB[1:0] BPIB[1:0] BPRO[1:0] BPRA[1:0] Value after reset: Symbol Bit Name Description b1, b0 BPRA[1:0] Memory Bus 1 (RAM) Priority R/(W) b1 b0 0 0: The order of priority is fixed.
Page 259 RX110 Group 15. Buses BPGB[1:0] Bits (Internal Peripheral Bus 2 Priority Control) These bits specify the priority order for internal peripheral bus 2. When the priority order is fixed, internal main bus 2 has priority over internal main bus 1. When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.
Page 260: Bus Error Monitoring Section
RX110 Group 15. Buses 15.4 Bus Error Monitoring Section The bus error monitoring section monitors the individual areas for bus errors, and when a bus error occurs, the error is indicated to the bus master. 15.4.1 Type of Bus Error There is a illegal address access bus error.
Page 261: Conditions Leading To Bus Errors
RX110 Group 15. Buses 15.4.3 Conditions Leading to Bus Errors Table 15.5 lists the type of bus errors for each area in the respective address space. If an illegal address access error is detected when no bus error has occurred (bus error status register n (BERSRn; n = 1, 2) is cleared), the detected error is reflected in the BERSRn register.
Page 262: Data Transfer Controller (Dtca)
RX110 Group 16. Data Transfer Controller (DTCa) Data Transfer Controller (DTCa) This MCU incorporates a data transfer controller (DTC). The DTC is activated by an interrupt request to perform data transfers. 16.1 Overview Table 16.1 lists the specifications of the DTC, and Figure 16.1 shows a block diagram of the DTC. Table 16.1 DTC Specifications Item...
Page 263 RX110 Group 16. Data Transfer Controller (DTCa) Register Vector number control Interrupt controller Activation Activation request control DTC response Bus interface DTCCR DTCVBR response DTCADMOD control DTCST DTCSTS Internal peripheral bus 1 Internal main bus 2 Internal main bus 1 Internal Memory bus 1 Memory bus 2...
Page 264: Register Descriptions
RX110 Group 16. Data Transfer Controller (DTCa) 16.2 Register Descriptions Registers MRA, MRB, SAR, DAR, CRA, and CRB are DTC internal registers, which cannot be directly accessed from the CPU. Values to be set in these DTC internal registers are placed in the RAM area as transfer information. When an activation request is generated, the DTC reads the transfer information from the RAM area and set them in the internal registers.
Page 265: Dtc Mode Register B (Mrb)
RX110 Group 16. Data Transfer Controller (DTCa) 16.2.2 DTC Mode Register B (MRB) Address(es): (inaccessible directly from the CPU) CHNE CHNS DISEL DM[1:0] — — Value after reset: x: Undefined Symbol Bit Name Description b1, b0 — Reserved These bits are read as undefined. The write value should be 0. —...
Page 266: Dtc Transfer Source Register (Sar)
RX110 Group 16. Data Transfer Controller (DTCa) 16.2.3 DTC Transfer Source Register (SAR) Address(es): (inaccessible directly from the CPU) Value after reset: Value after reset: x: Undefined SAR register is used to set the transfer source start address. In full-address mode, 32 bits are valid. In short-address mode, lower 24 bits are valid and upper 8 bits (b31 to b24) are ignored.
Page 267: Dtc Transfer Count Register A (Cra)
RX110 Group 16. Data Transfer Controller (DTCa) 16.2.5 DTC Transfer Count Register A (CRA) Address(es): (inaccessible directly from the CPU)  Normal transfer mode Value after reset:  Repeat transfer mode/block transfer mode CRAH CRAL Value after reset: x: Undefined Symbol Register Name Description...
Page 268: Dtc Transfer Count Register B (Crb)
RX110 Group 16. Data Transfer Controller (DTCa) 16.2.6 DTC Transfer Count Register B (CRB) Address(es): (inaccessible directly from the CPU) Value after reset: x: Undefined CRB register is used to set the block transfer count for block transfer mode. The transfer count is 1, 65535, and 65536 when the set value is 0001h, FFFFh, and 0000h, respectively. The CRB value is decremented (–1) when the final data of a single block size is transferred.
Page 269: Dtc Vector Base Register (Dtcvbr)
RX110 Group 16. Data Transfer Controller (DTCa) 16.2.8 DTC Vector Base Register (DTCVBR) Address(es): DTC.DTCVBR 0008 2404h Value after reset: Value after reset: DTCVBR register is used to set the base address for calculating the DTC vector table address. Writing to the upper 4 bits (b31 to b28) is ignored, and the address of this register is extended by the value specified by b27.
Page 270: Dtc Module Start Register (Dtcst)
RX110 Group 16. Data Transfer Controller (DTCa) 16.2.10 DTC Module Start Register (DTCST) Address(es): DTC.DTCST 0008 240Ch — — — — — — — DTCST Value after reset: Symbol Bit Name Description DTCST DTC Module Start 0: DTC module stop 1: DTC module start b7 to b1 —...
Page 271: Dtc Status Register (Dtcsts)
RX110 Group 16. Data Transfer Controller (DTCa) 16.2.11 DTC Status Register (DTCSTS) Address(es): DTC.DTCSTS 0008 240Eh — — — — — — — VECN[7:0] Value after reset: Symbol Bit Name Description b7 to b0 VECN[7:0] DTC-Activating Vector These bits indicate the vector number for the activation source Number Monitoring when DTC transfer is in progress.
Page 272: Activation Sources
RX110 Group 16. Data Transfer Controller (DTCa) 16.3 Activation Sources The DTC is activated by an interrupt request. Setting the ICU.DTCERn.DTCE bit (n = interrupt vector number) to 1 selects the corresponding interrupt as an activation source for the DTC. For the correspondence between the DTC activation sources and the vector addresses, refer to section 14.3.1, Interrupt Vector Table in section 14, Interrupt Controller (ICUb) .
Page 273 RX110 Group 16. Data Transfer Controller (DTCa) Upper: DTCVBR DTC vector table Lower: Vector number  4 Transfer information (1) DTC vector address Transfer information (1) start address Transfer information (2) start address Transfer information (2) Transfer information (n) start address 4 bytes Transfer information (n) 4 bytes...
Page 274: Operation
RX110 Group 16. Data Transfer Controller (DTCa) 16.4 Operation The DTC transfers data in accordance with the transfer information. Storage of the transfer information in the RAM area is required before DTC operation. When the DTC is activated, it reads the DTC vector corresponding to the vector number. Next, the DTC reads transfer information from the transfer information store address pointed by the DTC vector, transfers data, and then writes back the transfer information after the data transfer.
Page 275 RX110 Group 16. Data Transfer Controller (DTCa) Start Match and RRS bit = 1 Compare vector numbers. Match? Mismatch or RRS bit = 0 Read DTC vector Next transfer Read information to be transferred Update transfer information start address CHNE bit = 1? CHNS bit = 0 MD[1:0] bits = 01b? (Repeat transfer mode?)
Page 276: Transfer Information Read Skip Function
RX110 Group 16. Data Transfer Controller (DTCa) Table 16.3 Chain Transfer Conditions First Transfer Second Transfer* CHNE CHNS DISEL Transfer CHNE CHNS DISEL Transfer Counter* Counter* DTC Transfer Other than (1 → 0) — — — — — Ends after the first transfer (1 →...
Page 277: Transfer Information Write-Back Skip Function
RX110 Group 16. Data Transfer Controller (DTCa) 16.4.2 Transfer Information Write-Back Skip Function When the MRA.SM[1:0] bits or the MRB.DM[1:0] bits are set to “address fixed”, a part of transfer information is not written back. This function is performed independently of the setting of short-address mode or full-address mode. Table 16.4 lists transfer information write-back skip conditions and applicable registers.
Page 278: Normal Transfer Mode
RX110 Group 16. Data Transfer Controller (DTCa) 16.4.3 Normal Transfer Mode This mode allows 1-byte, 1-word, or 1-longword data transfer on a single activation source. The transfer count can be set to 1 to 65536. Transfer source addresses and transfer destination addresses can be set to increment, decrement, or fixed independently. This mode enables an interrupt request to the CPU to be generated at the end of specified-count transfer.
Page 279: Repeat Transfer Mode
RX110 Group 16. Data Transfer Controller (DTCa) 16.4.4 Repeat Transfer Mode This mode allows 1-byte, 1-word, or 1-longword data transfer on a single activation source. Specify either transfer source or transfer destination for the repeat area by the MRB.DTS bit. The transfer count can be set to 1 to 256.
Page 280: Block Transfer Mode
RX110 Group 16. Data Transfer Controller (DTCa) 16.4.5 Block Transfer Mode This mode allows single-block data transfer on a single activation source. Specify either transfer source or transfer destination for the block area by the MRB.DTS bit. The block size can be set to 1 to 256 bytes, 1 to 256 words, or 1 to 256 longwords.
Page 281: Chain Transfer
RX110 Group 16. Data Transfer Controller (DTCa) 16.4.6 Chain Transfer Setting the MRB.CHNE bit to 1 allows chain transfer to be performed continuously on a single activation source. If the MRB.CHNE and CHNS bits are set to 1 and 0, respectively, an interrupt request to the CPU is not generated by completion of specified number of rounds of transfer or by setting the MRB.DISEL bit to 1 (an interrupt request to the CPU is generated each time DTC data transfer is performed), and data transfer has no effect on the interrupt status flag of the activation source.
Page 282: Operation Timing
RX110 Group 16. Data Transfer Controller (DTCa) 16.4.7 Operation Timing Figure 16.9 to Figure 16.13 show examples of DTC operation timing. System clock ICU.IRn DTC activation request DTC access Transfer Data Vector read Transfer information read transfer information write n = Vector number Figure 16.9 Example (1) of DTC Operation Timing (Short-Address Mode, Normal Transfer Mode, Repeat Transfer Mode)
Page 283 RX110 Group 16. Data Transfer Controller (DTCa) System clock ICU.IRn DTC activation request DTC access Data Data Vector read Transfer Transfer Transfer Transfer transfer transfer information read information information information write read write n = Vector number Figure 16.11 Example (3) of DTC Operation Timing (Short-Address Mode, Chain Transfer) System clock ICU.IRn DTC activation request...
Page 284 RX110 Group 16. Data Transfer Controller (DTCa) System clock ICU.IRn DTC activation request Read skip enable DTC access Data Transfer Vector read Transfer Data Transfer transfer information write information read information write transfer n = Vector number Note: When activation sources (vector numbers) of (1) and (2) are the same and the RRS bit = 1, the transfer information read for request (2) is skipped.
Page 285: Execution Cycles Of The Dtc
RX110 Group 16. Data Transfer Controller (DTCa) 16.4.8 Execution Cycles of the DTC Table 16.8 lists the execution cycles of single data transfer of the DTC. For the order of the execution states, refer to section 16.4.7, Operation Timing . Table 16.8 Execution Cycles of the DTC Data Transfer...
Page 286: Dtc Setting Procedure
RX110 Group 16. Data Transfer Controller (DTCa) 16.5 DTC Setting Procedure Before using the DTC, set the DTC vector base register (DTCVBR). Figure 16.14 shows the procedure to set the DTC. Set the ICU.IERm.IENj bit corresponding to the activation Start source interrupt to 0 and provide the following settings.
Page 287: Examples Of Dtc Usage
RX110 Group 16. Data Transfer Controller (DTCa) 16.6 Examples of DTC Usage 16.6.1 Normal Transfer As an example of DTC usage, its employment in the reception of 128 bytes of data by an SCI is described below. (1) Transfer Information Setting In the MRA register, select a fixed source address (MRA.SM[1:0] bits = 00b), normal transfer mode (MRA.MD[1:0] bits = 00b), and byte-sized transfer (MRA.SZ[1:0] bits = 00b).
Page 288: Chain Transfer When The Counter = 0
RX110 Group 16. Data Transfer Controller (DTCa) 16.6.2 Chain Transfer When the Counter = 0 The second data transfer is performed only when the transfer counter is set to 0 in the first data transfer, and the first data transfer information is repeatedly changed in the second transfer. Repeating this chain transfer enables transfers to be repeated 256 times or more.
Page 289: Interrupt Source
RX110 Group 16. Data Transfer Controller (DTCa) Input circuit Transfer information allocated in the on-chip memory space Input buffer First data transfer Transfer information Chain transfer (counter = 0) Second data transfer Transfer information Upper 8 bits of DAR Figure 16.15 Chain Transfer When the Counter = 0 16.7 Interrupt Source...
Page 290: Low Power Consumption Function
RX110 Group 16. Data Transfer Controller (DTCa) 16.8 Low Power Consumption Function Before making a transition to the module stop state, deep sleep mode, or software standby mode, set the DTCST.DTCST bit to 0 (DTC module stop), and then perform the following. (1) Module Stop Function Writing 1 (transition to the module-stop state is made) to the MSTPCRA.MSTPA28 bit enables the module stop function of the DTC.
Page 291: Usage Notes
RX110 Group 16. Data Transfer Controller (DTCa) 16.9 Usage Notes 16.9.1 Transfer Information Start Address Be sure to set multiples of 4 for the transfer information start addresses in the vector table. Otherwise, such addresses are accessed with their lowest 2 bits regarded as 00b. 16.9.2 Allocating Transfer Information Allocate transfer data in the memory area according to the endian of the area as shown in Figure 16.16 .
Page 292: I/O Ports
RX110 Group 17. I/O Ports I/O Ports 17.1 Overview The I/O ports can function as general I/O ports, I/O pins of a peripheral module, or as input pins for an interrupt. Each pin can also be configured as an I/O pin of a peripheral module or as an input pin for an interrupt. Immediately after a reset, all pins function as input pins, and pin functions are switched by register settings.
Page 293 RX110 Group 17. I/O Ports Table 17.2 Port Functions Port Port Register Input Pull-up Open Drain Output 5-V Tolerant I/O Level ○ ― PORT0 P03, P05 — ○ ○ ― PORT1 P14, P15 ○ ○ ○ P16, P17 ○ ○ ―...
Page 294: I/O Port Configuration
RX110 Group 17. I/O Ports 17.2 I/O Port Configuration Port 4: P40 to P44, P46 PODR Reading the port ASEL bit Analog input Port 0: P03, P05 1: ON 0: OFF PODR Reading the port ASEL bit Analog output Figure 17.1 I/O Port Configuration (1) R01UH0421EJ0120 Rev.1.20 Page 294 of 968...
Page 295 RX110 Group 17. I/O Ports Port 1: P14 to P17 Port 2: P26 1: ON Port 3: P30 to P32 0: OFF Port A: PA0, PA1, PA3, PA4, PA6 Port B: PB0, PB1, PB3, PB5 to PB7 ODR0, ODR1 Port C: PC0 to PC7 Enable peripheral module output PODR Peripheral module output signal...
Page 296 RX110 Group 17. I/O Ports Port 5: P54, P55 1 : ON Port H: PH0 to PH3 0 : OFF Enable peripheral module output PODR Peripheral module output signal Input signal of peripheral module/interrupt Reading the port ISEL bit Note 1. An external interrupt function is multiplexed on this pin Port 3: P35 NMI input signal Reading the port...
Page 297 RX110 Group 17. I/O Ports Port H: PH7 XCIN/PH7 Reading the port RCR3.RTCEN SOSCCR.SOSTP RCR3.RTCEN SOSCCR.SOSTP 0 : OFF 1 : ON Sub clock XCOUT Figure 17.4 I/O Port Configuration (4) Port J: PJ6/VREFH0, PJ7/VREFL0 PODR Reading the port ASEL bit AVCC0 Note 1.
Page 298: Register Descriptions
RX110 Group 17. I/O Ports 17.3 Register Descriptions 17.3.1 Port Direction Register (PDR) Address(es): PORT0.PDR 0008 C000h, PORT1.PDR 0008 C001h, PORT2.PDR 0008 C002h, PORT3.PDR 0008 C003h, PORT4.PDR 0008 C004h, PORT5.PDR 0008 C005h, PORTA.PDR 0008 C00Ah, PORTB.PDR 0008 C00Bh, PORTC.PDR 0008 C00Ch, PORTE.PDR 0008 C00Eh, PORTH.PDR 0008 C011h, PORTJ.PDR 0008 C012h Value after reset: Symbol Bit Name...
Page 299: Port Output Data Register (Podr)
RX110 Group 17. I/O Ports 17.3.2 Port Output Data Register (PODR) Address(es): PORT0.PODR 0008 C020h, PORT1.PODR 0008 C021h, PORT2.PODR 0008 C022h, PORT3.PODR 0008 C023h, PORT4.PODR 0008 C024h, PORT5.PODR 0008 C025h, PORTA.PODR 0008 C02Ah, PORTB.PODR 0008 C02Bh, PORTC.PODR 0008 C02Ch, PORTE.PODR 0008 C02Eh, PORTH.PODR 0008 C031h, PORTJ.PODR 0008 C032h Value after reset: Symbol Bit Name...
Page 300: Port Input Data Register (Pidr)
RX110 Group 17. I/O Ports 17.3.3 Port Input Data Register (PIDR) Address(es): PORT0.PIDR 0008 C040h, PORT1.PIDR 0008 C041h, PORT2.PIDR 0008 C042h, PORT3.PIDR 0008 C043h, PORT4.PIDR 0008 C044h, PORT5.PIDR 0008 C045h, PORTA.PIDR 0008 C04Ah, PORTB.PIDR 0008 C04Bh, PORTC.PIDR 0008 C04Ch, PORTE.PIDR 0008 C04Eh, PORTH.PIDR 0008 C051h, PORTJ.PIDR 0008 C052h Value after reset: x: Undefined Symbol...
Page 301: Port Mode Register (Pmr)
RX110 Group 17. I/O Ports 17.3.4 Port Mode Register (PMR) Address(es): PORT0.PMR 0008 C060h, PORT1.PMR 0008 C061h, PORT2.PMR 0008 C062h, PORT3.PMR 0008 C063h, PORT4.PMR 0008 C064h, PORT5.PMR 0008 C065h, PORTA.PMR 0008 C06Ah, PORTB.PMR 0008 C06Bh, PORTC.PMR 0008 C06Ch, PORTE.PMR 0008 C06Eh, PORTH.PMR 0008 C071h, PORTJ.PMR 0008 C072h Value after reset: Symbol Bit Name...
Page 302: Open Drain Control Register 0 (Odr0)
RX110 Group 17. I/O Ports 17.3.5 Open Drain Control Register 0 (ODR0) Address(es): PORT3.ODR0 0008 C086h, PORTA.ODR0 0008 C094h, PORTB.ODR0 0008 C096h, PORTC.ODR0 0008 C098h, PORTE.ODR0 0008 C09Ch Value after reset: Symbol Bit Name Description Pm0 Output Type Select 0: CMOS output 1: N-channel open-drain output Reserved This bit is read as 0.
Page 303: Open Drain Control Register 1 (Odr1)
RX110 Group 17. I/O Ports 17.3.6 Open Drain Control Register 1 (ODR1) Address(es): PORT1.ODR1 0008 C083h, PORT2.ODR1 0008 C085h, PORTA.ODR1 0008 C095h, PORTB.ODR1 0008 C097h, PORTC.ODR1 0008 C099h, PORTE.ODR1 0008 C09Dh Value after reset: Symbol Bit Name Description  PA4, PC4, PE4 Pm4 Output Type Select b0 0: CMOS output 1: N-channel open-drain...
Page 304: Pull-Up Control Register (Pcr)
RX110 Group 17. I/O Ports 17.3.7 Pull-Up Control Register (PCR) Address(es): PORT0.PCR 0008 C0C0h, PORT1.PCR 0008 C0C1h, PORT2.PCR 0008 C0C2h, PORT3.PCR 0008 C0C3h, PORT5.PCR 0008 C0C5h, PORTA.PCR 0008 C0CAh, PORTB.PCR 0008 C0CBh, PORTC.PCR 0008 C0CCh, PORTE.PCR 0008 C0CEh, PORTH.PCR 0008 C0D1h Value after reset: Symbol Bit Name...
Page 305: Port Switching Register A (Psra)
RX110 Group 17. I/O Ports 17.3.8 Port Switching Register A (PSRA) Address(es): PORT.PSRA 0008 C121h PSEL7 PSEL6 — — — — — — Value after reset: Symbol Bit Name Description b5 to b0 — Reserved This bit is read as 0. The write value should be 0. PSEL6 PB6/PC0 Switching 0: PB6 general I/O port function is selected...
Page 306: Port Switching Register B (Psrb)
RX110 Group 17. I/O Ports 17.3.9 Port Switching Register B (PSRB) Address(es): PORT.PSRB 0008 C120h — — PSEL5 — PSEL3 — PSEL1 PSEL0 Value after reset: Symbol Bit Name Description PSEL0 PB0/PC0 Switching 0: PB0 general I/O port function is selected 1: PC0 general I/O port function is selected PSEL1 PB1/PC1 Switching...
Page 307: Initialization Of The Port Direction Register (Pdr)
RX110 Group 17. I/O Ports 17.4 Initialization of the Port Direction Register (PDR) Initialize reserved bits in the PDR register according to Table 17.3 to Table 17.6 .  The blank columns in Table 17.3 to Table 17.6 indicate the bits corresponding to the pins listed in Table 17.1 , I/O Port Specifications .
Page 308 RX110 Group 17. I/O Ports Table 17.5 PDR Register Settings in 40-Pin Packages PDR Register Port Symbol PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORTA PORTB PORTC PORTE PORTH PORTJ Table 17.6 PDR Register Settings in 36-Pin Packages PDR Register Port Symbol PORT0 PORT1 PORT2...
Page 309: Handling Of Unused Pins
RX110 Group 17. I/O Ports 17.5 Handling of Unused Pins The handling of unused pins is listed in Table 17.7 . Table 17.7 Handling of Unused Pins Pin Name Description (Always used as mode pins) RES# Connect this pin to VCC via a pull-up resistor. P35/NMI Connect this pin to VCC via a pull-up resistor.
Page 310: Multi-Function Pin Controller (Mpc)
RX110 Group 18. Multi-Function Pin Controller (MPC) Multi-Function Pin Controller (MPC) 18.1 Overview The multi-function pin controller (MPC) is used to allocate input and output signals for peripheral modules and input interrupt signals to pins from among multiple ports. Table 18.1 shows the allocation of pin functions to multiple pins. A and N/A in the table indicate whether the pins are available or not available on the given package.
Page 311 RX110 Group 18. Multi-Function Pin Controller (MPC) Table 18.1 Allocation of Pin Functions to Multiple Pins (2/5) Package Module/Function Channel Pin Functions Allocation Port 64-pin 48-pin 40-pin 36-pin Multi-function timer unit 2 MTU1 MTIOC1A (I/O) MTIOC1B (I/O) MTU2 MTIOC2A (I/O) MTIOC2B (I/O) MTU5 MTIC5U (input)
Page 312 RX110 Group 18. Multi-Function Pin Controller (MPC) Table 18.1 Allocation of Pin Functions to Multiple Pins (3/5) Package Module/Function Channel Pin Functions Allocation Port 64-pin 48-pin 40-pin 36-pin Serial communications interface SCI1 RXD1 (input)/ SMISO1 (I/O)/ SSCL1 (I/O) TXD1 (output)/ SMOSI1 (I/O)/ SSDA1 (I/O) SCK1 (I/O)
Page 313 RX110 Group 18. Multi-Function Pin Controller (MPC) Table 18.1 Allocation of Pin Functions to Multiple Pins (4/5) Package Module/Function Channel Pin Functions Allocation Port 64-pin 48-pin 40-pin 36-pin Serial peripheral interface RSPI0 RSPCKA (I/O) MOSIA (I/O) MISOA (I/O) SSLA0 (I/O) SSLA1 (output) SSLA2 (output) SSLA3 (output)
Page 314 RX110 Group 18. Multi-Function Pin Controller (MPC) Table 18.1 Allocation of Pin Functions to Multiple Pins (5/5) Package Module/Function Channel Pin Functions Allocation Port 64-pin 48-pin 40-pin 36-pin Clock frequency accuracy measurement CACREF (input) circuit Voltage detection circuit CMPA2 (input) Note 1.
Page 315: Register Descriptions
RX110 Group 18. Multi-Function Pin Controller (MPC) 18.2 Register Descriptions Registers and bits for pins that are not present due to differences according to the package are reserved. Write the value after a reset when writing to such bits. 18.2.1 Write-Protect Register (PWPR) Address(es): 0008 C11Fh B0WI PFSWE...
Page 316: P1N Pin Function Control Register (P1Npfs) (N = 4 To 7)
RX110 Group 18. Multi-Function Pin Controller (MPC) 18.2.2 P1n Pin Function Control Register (P1nPFS) (n = 4 to 7) Address(es): P14PFS 0008 C14Ch, P15PFS 0008 C14Dh, P16PFS 0008 C14Eh, P17PFS 0008 C14Fh — ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0...
Page 317 RX110 Group 18. Multi-Function Pin Controller (MPC) Table 18.2 Register Settings for I/O Pin Functions in 64-Pin and 48-Pin PSEL[4:0] Settings 00000b Hi-Z (initial value) 00001b — MTIOC0B — — 00010b MTCLKA MTCLKB — — 00011b MTIOC0A — — MTIOC0C 00111b —...
Page 318: P2N Pin Function Control Register (P2Npfs) (N = 6 To 7)
RX110 Group 18. Multi-Function Pin Controller (MPC) 18.2.3 P2n Pin Function Control Register (P2nPFS) (n = 6 to 7) Address(es): P26PFS 0008 C156h, P27PFS 0008 C157h ASEL ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function.
Page 319: P3N Pin Function Control Register (P3Npfs) (N = 0 To 2)
RX110 Group 18. Multi-Function Pin Controller (MPC) 18.2.4 P3n Pin Function Control Register (P3nPFS) (n = 0 to 2) Address(es): P30PFS 0008 C158h, P31PFS 0008 C159h, P32PFS 0008 C15Ah — ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 PSEL[4:0] Pin Function Select...
Page 320: P4N Pin Function Control Register (P4Npfs) (N = 0 To 4, 6)
RX110 Group 18. Multi-Function Pin Controller (MPC) 18.2.5 P4n Pin Function Control Register (P4nPFS) (n = 0 to 4, 6) Address(es): P40PFS 0008 C160h, P41PFS 0008 C161h, P42PFS 0008 C162h, P43PFS 0008 C163h, P44PFS 0008 C164h, P46PFS 0008 C166h ASEL —...
Page 321: Pan Pin Function Control Register (Panpfs) (N = 0, 1, 3, 4, 6)
RX110 Group 18. Multi-Function Pin Controller (MPC) 18.2.6 PAn Pin Function Control Register (PAnPFS) (n = 0, 1, 3, 4, 6) Address(es): PA0PFS 0008 C190h, PA1PFS 0008 C191h, PA3PFS 0008 C193h, PA4PFS 0008 C194h, PA6PFS 0008 C196h — ISEL — PSEL[4:0] Value after reset: Symbol...
Page 322 RX110 Group 18. Multi-Function Pin Controller (MPC) Table 18.9 Register Settings for I/O Pin Function in 48-Pin PSEL[4:0] Settings 00000b Hi-Z (initial value) 00001b MTIOC0B MTIOC0D MTIC5U MTIC5V 00010b MTCLKC MTCLKD MTCLKA MTCLKB 00011b — MTIOC1B MTIOC2B MTIOC2A 00111b RTCOUT —...
Page 323 RX110 Group 18. Multi-Function Pin Controller (MPC) Table 18.11 Register Settings for I/O Pin Function in 36-Pin PSEL[4:0] Settings 00000b Hi-Z (initial value) 00001b MTIOC0D MTIC5U MTIC5V 00010b MTCLKD MTCLKA MTCLKB 00011b MTIOC1B MTIOC2B MTIOC2A 01010b RXD5 TXD5 — SMISO5 SMOSI5 SSCL5 SSDA5...
Page 324: Pbn Pin Function Control Register (Pbnpfs) (N = 0, 1, 3, 5 To 7)
RX110 Group 18. Multi-Function Pin Controller (MPC) 18.2.7 PBn Pin Function Control Register (PBnPFS) (n = 0, 1, 3, 5 to 7) Address(es): PB0PFS 0008 C198h, PB1PFS 0008 C199h, PB3PFS 0008 C19Bh, PB5PFS 0008 C19Dh, PB6PFS 0008 C19Eh, PB7PFS 0008 C19Fh —...
Page 325 RX110 Group 18. Multi-Function Pin Controller (MPC) Table 18.13 Register Settings for I/O Pin Function in 48-Pin PSEL[4:0] Settings 00000b Hi-Z (initial value) 00001b MTIC5W MTIOC0C MTIOC0A MTIOC2A 00010b MTIOC0C — — MTIOC1B 00111b RTCOUT — — — 01001b ADTRG0# —...
Page 326: Pcn Pin Function Control Register (Pcnpfs) (N = 2 To 7)
RX110 Group 18. Multi-Function Pin Controller (MPC) 18.2.8 PCn Pin Function Control Register (PCnPFS) (n = 2 to 7) Address(es): PC2PFS 0008 C1A2h, PC3PFS 0008 C1A3h, PC4PFS 0008 C1A4h, PC5PFS 0008 C1A5h, PC6PFS 0008 C1A6h, PC7PFS 0008 C1A7h — ISEL —...
Page 327 RX110 Group 18. Multi-Function Pin Controller (MPC) Table 18.16 Register Settings for I/O Pin Function in 48-Pin PSEL[4:0] Settings 00000b Hi-Z (initial value) 00010b MTCLKC MTCLKD MTCLKA MTCLKB 00111b — — — CACREF 01001b CLKOUT — — — 01010b SCK5 —...
Page 328: Pen Pin Function Control Register (Penpfs) (N = 0 To 7)
RX110 Group 18. Multi-Function Pin Controller (MPC) 18.2.9 PEn Pin Function Control Register (PEnPFS) (n = 0 to 7) Address(es): PE0PFS 0008 C1B0h, PE1PFS 0008 C1B1h, PE2PFS 0008 C1B2h, PE3PFS 0008 C1B3h, PE4PFS 0008 C1B4h, PE5PFS 0008 C1B5h, PE6PFS 0008 C1B6h, PE7PFS 0008 C1B7h ASEL ISEL —...
Page 329 RX110 Group 18. Multi-Function Pin Controller (MPC) Table 18.19 Register Settings for I/O Pin Function in 48-Pin PSEL[4:0] Settings 00000b Hi-Z (initial value) 00010b MTIOC2A — — MTIOC1B MTIOC1A — 00011b — — — MTIOC0A — — 01100b SCK12 TXD12 RXD12 CTS12# —...
Page 330: Phn Pin Function Control Register (Phnpfs) (N = 0 To 3)
RX110 Group 18. Multi-Function Pin Controller (MPC) 18.2.10 PHn Pin Function Control Register (PHnPFS) (n = 0 to 3) Address(es): PH0PFS 0008 C1C8h, PH1PFS 0008 C1C9h, PH2PFS 0008 C1CAh, PH3PFS 0008 C1CBh — ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0...
Page 331: Pjn Pin Function Control Register (Pjnpfs) (N = 6, 7)
RX110 Group 18. Multi-Function Pin Controller (MPC) 18.2.11 PJn Pin Function Control Register (PJnPFS) (n = 6, 7) Address(es): PJ6PFS 0008 C1D6h, PJ7PFS 0008 C1D7h ASEL — — — — — — — Value after reset: Symbol Bit Name Description b6 to b0 —...
Page 332: Usage Notes
RX110 Group 18. Multi-Function Pin Controller (MPC) 18.3 Usage Notes 18.3.1 Procedure for Specifying I/O Pin Functions Use the following procedure to specify the I/O pin functions. 1. Set the port mode register (PMR) to 0 to select the general I/O port function. 2.
Page 333: Note On Using Analog Functions
RX110 Group 18. Multi-Function Pin Controller (MPC) 5. Points to note regarding the port mode register (PMR), port direction register (PDR), and Pmn pin function control register (PmnPFS) settings for pins that have multiplexed pin functions are listed in Table 18.22 . Table 18.22 Register Settings PmnPFS...
Page 334: Multi-Function Timer Pulse Unit 2 (Mtu2B)
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) Multi-Function Timer Pulse Unit 2 (MTU2b) In this section, “PCLK” is used to refer to PCLKB. 19.1 Overview This MCU has an on-chip multi-function timer pulse unit 2 (MTU). Each unit comprises a 16-bit timer with four channels (MTU0 to MTU2, MTU5).
Page 335 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) Table 19.2 MTU Functions Item MTU0 MTU1 MTU2 MTU5 Count clock PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/64 PCLK/64 PCLK/64 PCLK/64 MTCLKA PCLK/256 PCLK/1024 MTCLKB MTCLKA MTCLKA MTCLKC...
Page 336 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) Input pins MTU5: TGIU5 MTU5: MTIC5U TGIV5 MTIC5V TGIW5 MTIC5W Clock input Internal peripheral bus Internal clock: PCLK/1 PCLK/4 PCLK/16 A/D converter start request signals PCLK/64 PCLK/256 MTU0 to 2: TRGAN PCLK/1024 MTU0: TRG0AN...
Page 337 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) Table 19.3 lists the I/O pins to be used by the MTU. Table 19.3 MTU I/O Pins Module Symbol Pin Name Function MTCLKA Input External clock A input pin (MTU1 phase counting mode A phase input) MTCLKB Input External clock B input pin (MTU1 phase counting mode B phase input)
Page 338: Register Descriptions
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.2 Register Descriptions 19.2.1 Timer Control Register (TCR)  MTU0.TCR, MTU1.TCR, MTU2.TCR Address(es): MTU0.TCR 0008 8700h, MTU1.TCR 0008 8780h, MTU2.TCR 0008 8800h CCLR[2:0] CKEG[1:0] TPSC[2:0] Value after reset: Symbol Bit Name Description b2 to b0 TPSC[2:0]...
Page 339 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) CCLR[2:0] Bits (Counter Clear) These bits select the TCNT counter clearing source. Refer to Table 19.4 and Table 19.5 for details. Table 19.4 CCLR[2:0] (MTU0) Bit 7 Bit 6 Bit 5 Channel CCLR[2] CCLR[1]...
Page 340 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) Table 19.7 TPSC[2:0] (MTU1) Bit 2 Bit 1 Bit 0 Channel TPSC[2] TPSC[1] TPSC[0] Description MTU1 Internal clock: counts on PCLK/1 Internal clock: counts on PCLK/4 Internal clock: counts on PCLK/16 Internal clock: counts on PCLK/64 External clock: counts on MTCLKA pin input External clock: counts on MTCLKB pin input...
Page 341: Timer Mode Register (Tmdr)
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.2.2 Timer Mode Register (TMDR) Address(es): MTU0.TMDR 0008 8701h, MTU1.TMDR 0008 8781h, MTU2.TMDR 0008 8801h — MD[3:0] Value after reset: Symbol Bit Name Description b3 to b0 MD[3:0] Mode Select These bits specify the timer operating mode. Refer to Table 19.10 for details.
Page 342 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) BFE Bit (Buffer Operation E) This bit specifies normal operation or buffered operation for registers MTU0.TGRE and MTU0.TGRF. Compare match with the TGRF register occurs even when the TGRF register is used as a buffer register. In MTU1 to MTU2, this bit is reserved.
Page 343: Timer I/O Control Register (Tior)
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.2.3 Timer I/O Control Register (TIOR)  MTU0.TIORH, MTU1.TIOR, MTU2.TIOR Address(es): MTU0.TIORH 0008 8702h, MTU1.TIOR 0008 8782h, MTU2.TIOR 0008 8802h IOB[3:0] IOA[3:0] Value after reset: Symbol Bit Name Description b3 to b0 IOA[3:0] I/O Control A Refer to the following tables.*...
Page 344 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b)  MTU5.TIORU, MTU5.TIORV, MTU5.TIORW Address(es): MTU5.TIORU 0008 8886h, MTU5.TIORV 0008 8896h, MTU5.TIORW 0008 88A6h — — — IOC[4:0] Value after reset: Symbol Bit Name Description b4 to b0 IOC[4:0] I/O Control C Refer to the following table.
Page 345 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) Table 19.12 TIORL (MTU0) Bit 7 Bit 6 Bit 5 Bit 4 Description IOD[3] IOD[2] IOD[1] IOD[0] MTU0.TGRD Function MTIOC0D Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 346 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) Table 19.14 TIOR (MTU2) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB[3] IOB[2] IOB[1] IOB[0] MTU2.TGRB Function MTIOC2B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 347 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) Table 19.16 TIORL (MTU0) Bit 3 Bit 2 Bit 1 Bit 0 Description IOC[3] IOC[2] IOC[1] IOC[0] MTU0.TGRC Function MTIOC0C Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 348 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) Table 19.18 TIOR (MTU2) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA[3] IOA[2] IOA[1] IOA[0] MTU2.TGRA Function MTIOC2A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 349: Timer Compare Match Clear Register (Tcntcmpclr)
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.2.4 Timer Compare Match Clear Register (TCNTCMPCLR) Address(es): MTU5.TCNTCMPCLR 0008 88B6h CMPCL CMPCL CMPCL — — — — — Value after reset: Symbol Bit Name Description CMPCLR5W TCNT Compare Clear 5W 0: Disables MTU5.TCNTW to be cleared to 0000h at MTU5.TCNTW and MTU5.TGRW compare match or input capture 1: Enables MTU5.TCNTW to be cleared to 0000h at MTU5.TCNTW...
Page 350: Timer Interrupt Enable Register (Tier)
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.2.5 Timer Interrupt Enable Register (TIER)  MTU0.TIER Address(es): MTU0.TIER 0008 8704h TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Value after reset:  MTU1.TIER, MTU2.TIER Address(es): MTU1.TIER 0008 8784h, MTU2.TIER 0008 8804h TTGE —...
Page 351 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) In MTU0, this bit is reserved. It is read as 0. The write value should be 0. TTGE Bit (A/D Converter Start Request Enable) This bit enables or disables generation of A/D converter start requests by the TGRA input capture/compare match. ...
Page 352: Timer Status Register (Tsr)
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.2.6 Timer Status Register (TSR) Address(es): MTU0.TSR 0008 8705h, MTU1.TSR 0008 8785h, MTU2.TSR 0008 8805h TCFD — — — — — — — Value after reset: x: Undefined Symbol Bit Name Description b5 to b0 —...
Page 353: Timer Buffer Operation Transfer Mode Register (Tbtm)
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.2.7 Timer Buffer Operation Transfer Mode Register (TBTM) Address(es): MTU0.TBTM 0008 8726h — — — — — TTSE TTSB TTSA Value after reset: Symbol Bit Name Description TTSA Timing Select A 0: When compare match A occurs in each channel, data is transferred from TGRC to TGRA 1: When TCNT is cleared in each channel, data is transferred from TGRC...
Page 354: Timer Input Capture Control Register (Ticcr)
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.2.8 Timer Input Capture Control Register (TICCR) Address(es): MTU1.TICCR 0008 8790h — — — — I2BE I2AE I1BE I1AE Value after reset: Symbol Bit Name Description I1AE Input Capture Enable 0: Does not include the MTIOC1A pin in the MTU2.TGRA input capture conditions 1: Includes the MTIOC1A pin in the MTU2.TGRA input capture conditions...
Page 355: Timer General Register (Tgr)
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.2.10 Timer General Register (TGR) Address(es): MTU0.TGRA 0008 8708h, MTU0.TGRB 0008 870Ah, MTU0.TGRC 0008 870Ch, MTU0.TGRD 0008 870Eh, MTU0.TGRE 0008 8720h, MTU0.TGRF 0008 8722h, MTU1.TGRA 0008 8788h, MTU1.TGRB 0008 878Ah, MTU2.TGRA 0008 8808h, MTU2.TGRB 0008 880Ah, MTU5.TGRU 0008 8882h, MTU5.TGRV 0008 8892h, MTU5.TGRW 0008 88A2h Value after reset: Note:...
Page 356: Timer Start Registers (Tstr)
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.2.11 Timer Start Registers (TSTR)  MTU.TSTR (MTU0 to MTU2) Address(es): MTU.TSTR 0008 8680h — — — — — CST2 CST1 CST0 Value after reset: Symbol Bit Name Description CST0 Counter Start 0 0: MTU0.TCNT performs count stop 1: MTU0.TCNT performs count operation CST1...
Page 357: Timer Synchronous Registers (Tsyr)
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.2.12 Timer Synchronous Registers (TSYR) Address(es): MTU.TSYR 0008 8681h — — — — — SYNC2 SYNC1 SYNC0 Value after reset: Symbol Bit Name Description SYNC0 Timer Synchronous Operation 0 0: MTU0.TCNT operates independently (TCNT setting/clearing is not related to other channels) 1: MTU0.TCNT performs synchronous operation.
Page 358: Noise Filter Control Registers (Nfcr)
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.2.13 Noise Filter Control Registers (NFCR)  MTU0.NFCR, MTU1.NFCR, MTU2.NFCR Address(es): MTU0.NFCR 0008 8690h, MTU1.NFCR 0008 8691h, MTU2.NFCR 0008 8692h — — NFCS[1:0] NFDEN NFCEN NFBEN NFAEN Value after reset: Symbol Bit Name Description NFAEN...
Page 359 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) NFCS[1:0] Bits (Noise Filter Clock Select) These bits set the sampling interval for the noise filters. When setting the NFCS[1:0] bits, wait for two cycles of the selected sampling interval before setting the input-capture function. When the NFCS[1:0] bits are set to 11b, selecting the external clock as the source to drive counting, wait for two cycles of the external clock before setting the input- capture function.
Page 360: Bus Master Interface
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.2.14 Bus Master Interface The timer counters (TCNT) and timer general registers (TGR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/write access. 8-bit read/write is not allowed. Access the registers in 16-bit units. All registers other than the above registers are 8-bit registers, so read/write access should be performed in 8-bit units.
Page 361: Operation
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.3 Operation 19.3.1 Basic Functions Each channel has the TCNT counter and the TGR register. The TCNT counter performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR register can be used as an input capture register or an output compare register.
Page 362 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (b) Free-Running Count Operation and Periodic Count Operation Immediately after a reset, the MTU’s TCNT counters are all designated as free-running counters. When the relevant CSTn bit in the TSTR register is set to 1, the corresponding TCNT counter starts up-count operation as a free-running counter.
Page 363 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (2) Waveform Output by Compare Match The MTU can output low or high or toggle output from the corresponding output pin using compare match. (a) Example of Procedure for Setting Waveform Output by Compare Match Figure 19.5 shows an example of the procedure for setting waveform output by compare match.
Page 364 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (b) Examples of Waveform Output Operation Figure 19.6 shows an example of low output and high output. In this example, the TCNT counter has been designated as a free-running counter, and settings have been made so that high is output by compare match A and low is output by compare match B.
Page 365 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (3) Input Capture Function The TCNT value can be transferred to the TGR register on detection of the input edge of the MTIOCnm (n = 0 to 2; m = A to D) pin and MTIC5m (m = W, V, U) pin. The rising edge, falling edge, or both edges can be selected as the detection edge.
Page 366 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (b) Example of Input Capture Operation Figure 19.9 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the MTIOCnA pin input capture input edge, the falling edge has been selected as the MTIOCnB pin input capture input edge, and counter clearing by the TGRB input capture has been designated for the TCNT counter.
Page 367: Synchronous Operation
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.3.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be modified simultaneously (synchronous setting). In addition, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in the TCR register.
Page 368 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (2) Example of Synchronous Operation Figure 19.11 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for MTU0 to MTU2, compare match of the MTU0.TGRB register has been set as the counter clearing source in MTU0, and synchronous clearing has been set for the counter clearing source in MTU1 and MTU2.
Page 369: Buffer Operation
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.3.3 Buffer Operation Buffer operation, provided for MTU0, enables registers TGRC and TGRD to be used as buffer registers. In MTU0, TGRF register can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register.
Page 370 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (1) Example of Buffer Operation Setting Procedure Figure 19.14 shows an example of the buffer operation setting procedure. [1] Designate the TGR register as an input capture Buffer operation register or output compare register by means of the TIOR register.
Page 371 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (b) When TGR register is an Input Capture Register Figure 19.16 shows an operation example in which the TGRA register has been designated as an input capture register, and buffer operation has been designated for registers TGRA and TGRC. Counter clearing by TGRA input capture has been set for the TCNT counter, and both rising and falling edges have been selected as the MTIOCnA pin input capture input edge.
Page 372 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (3) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for MTU0 by setting the timer buffer operation transfer mode registers (MTU0.TBTM).
Page 373: Cascaded Operation
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.3.4 Cascaded Operation In cascaded operation, 16-bit counters in different two channels are used together as a 32-bit counter. This function works when overflow/underflow of the MTU2.TCNT counter is selected as the count clock for MTU1 through the TCR.TPSC[2:0] bits.
Page 374 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (1) Example of Cascaded Operation Setting Procedure Figure 19.18 shows an example of the cascaded operation setting procedure. [1] Set the MTU1.TCR.TPSC[2:0] bits to 111b to Cascaded operation select MTU2.TCNT overflow/underflow counting. Set cascading [2] Set the TSTR.CST bit for the upper and lower channels to 1 to start the count operation.
Page 375 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (3) Cascaded Operation Example (b) Figure 19.20 illustrates the operation when counters MTU1.TCNT and MTU2.TCNT have been cascaded and the TICCR.I2AE bit has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the MTU1.TIOR.IOA[3:0] bits have selected the MTIOC1A rising edge for the input capture timing while the MTU2.TIOR.IOA[3:0] bits have selected the MTIOC2A rising edge for the input capture timing.
Page 376 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (4) Cascaded Operation Example (c) Figure 19.21 illustrates the operation when counters MTU1.TCNT and MTU2.TCNT have been cascaded and the I2AE and I1AE bits in TICCR register have been set to 1 to include the MTIOC2A and MTIOC1A pins in the MTU1.TGRA and MTU2.TGRA input capture conditions, respectively.
Page 377 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (5) Cascaded Operation Example (d) Figure 19.22 illustrates the operation when counters MTU1.TCNT and MTU2.TCNT have been cascaded and the TICCR.I2AE bit has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the MTU1.TIOR.IOA[3:0] bits have selected occurrence of MTU0.TGRA compare match or input capture for the input capture timing while the MTU2.TIOR.IOA[3:0] bits have selected the MTIOC2A rising edge for the input capture timing.
Page 378: Pwm Modes
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.3.5 PWM Modes PWM modes are provided to output PWM waveforms from the external pins. The output level can be selected as low, high, or toggle output in response to a compare match of each TGR register. PWM waveforms in the range of 0% to 100% duty cycle can be output according to the TGR settings.
Page 379 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (1) Example of PWM Mode Setting Procedure Figure 19.23 shows an example of the PWM mode setting procedure. PWM mode [1] Set the TCR.TPSC[2:0] bits to select the count clock source. Select count clock At the same time, set the TCR.CKEG[1:0] bits to select the clock edge.
Page 380 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) Figure 19.25 shows an example of operation in PWM mode 2. In this example, synchronous operation is designated for MTU0 and MTU1, MTU1.TGRB compare match is set as the TCNT clearing source, and a low level is set as the initial output value and a high level as the output value for the other TGR registers (MTU0.TGRA to MTU0.TGRD and MTU1.TGRA), outputting 5-phase PWM waveforms.
Page 381 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) Figure 19.26 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode 1. In this example, TGRA compare match is set as the TCNT clearing source, a low level is set as the initial output value and output value for the TGRA register, and a high level is set as the output value for the TGRB register.
Page 382: Phase Counting Mode
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.3.6 Phase Counting Mode When phase counting mode is specified, an external clock is selected as the count clock and the TCNT counter operates as an up-counter/down-counter regardless of the setting of the TCR.TPSC[2:0] bits and TCR.CKEG[1:0] bits. However, the functions of the TCR.CCLR[2:0] bits and of registers TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used.
Page 383 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (2) Examples of Phase Counting Mode Operation In phase counting mode, the TCNT counter is incremented or decremented according to the phase difference between two external clocks. There are four modes according to the count conditions. (a) Phase Counting Mode 1 Figure 19.28 shows an example of operation in phase counting mode 1, and Table 19.25 lists the TCNT up-counting and down-counting conditions.
Page 384 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (b) Phase Counting Mode 2 Figure 19.29 shows an example of operation in phase counting mode 2, and Table 19.26 lists the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value...
Page 385 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) Phase Counting Mode 3 Figure 19.30 shows an example of operation in phase counting mode 3, and Table 19.27 lists the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value Down-counting...
Page 386 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (d) Phase Counting Mode 4 Figure 19.31 shows an example of operation in phase counting mode 4, and Table 19.28 lists the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value...
Page 387 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (3) Phase Counting Mode Application Example Figure 19.32 shows an example in which MTU1 is in phase counting mode, and MTU1 is coupled with MTU0 to input 2-phase encoder pulses of a servo motor in order to detect position or speed. MTU1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to MTCLKA and MTCLKB.
Page 388: External Pulse Width Measurement
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.3.7 External Pulse Width Measurement Up to three external pulse widths can be measured in MTU5. When the IOC[4:0] bits in MTU5.TIORU, TIORV, and TIORW are set for pulse width measurement, the pulse width of the signal input to the MTIC5U, MTIC5V, and MTIC5W pins is measured.
Page 389: Noise Filter
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.3.8 Noise Filter Each pin for use in input capture and external pulse input to the MTU is equipped with a noise filter. The noise filter samples input signals at the sampling clock and removes the pulses of which length is less than three sampling cycles. The noise filter functionality includes enabling and disabling of the noise filter for each pin and setting of the sampling clock for each channel.
Page 390: Interrupt Sources
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.4 Interrupt Sources 19.4.1 Interrupt Sources and Priorities There are three interrupt sources; the TGR input capture/compare match, the TCNT counter overflow, and the TCNT counter underflow. Each interrupt source has its own enable/disable bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
Page 391: Dtc Activation
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.4.2 DTC Activation The DTC can be activated by the TGR input capture/compare match interrupt in each channel. For details, refer to section 16, Data Transfer Controller (DTCa) . The MTU provides a total of 11 input capture/compare match interrupts and overflow interrupts that can be used as DTC activation sources: four for MTU0, two each for MTU1 and MTU2, and three for MTU5.
Page 392: Operation Timing
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.5 Operation Timing 19.5.1 Input/Output Timing (1) TCNT Count Timing Figure 19.36 and Figure 19.37 show the TCNT count timing for TGI interrupt in internal clock operation, Figure 19.38 shows the TCNT count timing in external clock operation (normal mode), and Figure 19.39 shows the TCNT count timing in external clock operation (phase counting mode).
Page 393 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (2) Output Compare Output Timing A compare match signal is generated in the final state in which the TCNT counter and the TGR register match (the point at which the count value matched is updated by the TCNT counter). When a compare match signal is generated, the value set in the TIOR register is output to the output compare output pin (MTIOC pin).
Page 394 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 19.42 and Figure 19.43 show the timing when counter clearing on compare match is specified, and Figure 19.44 shows the timing when counter clearing on input capture is specified. PCLK Compare match signal Counter clear signal...
Page 395 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (5) Buffer Operation Timing Figure 19.45 to Figure 19.47 show the timing in buffer operation. PCLK TCNT n + 1 Compare match signal TGRA, TGRB TGRC, TGRD Figure 19.45 Buffer Operation Timing (Compare Match) PCLK Input capture signal TCNT...
Page 396: Interrupt Signal Timing
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.5.2 Interrupt Signal Timing (1) Timing for TGI Interrupt by Compare Match Figure 19.48 and Figure 19.49 show the TGI interrupt request signal timing on compare match. PCLK TCNT count clock N + 1 TCNT Compare match signal...
Page 397 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (2) Timing for TGI Interrupt by Input Capture Figure 19.50 and Figure 19.51 show TGI interrupt request signal timing on input capture. PCLK Input capture signal TCNT Interrupt signal Figure 19.50 TGI Interrupt Timing (Input Capture) (MTU0 to MTU2) PCLK Input capture signal...
Page 398 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (3) TCIV and TCIU Interrupt Timing Figure 19.52 shows the TCIV interrupt request signal timing on overflow. Figure 19.53 shows the TCIU interrupt request signal timing on underflow. PCLK TCNT count clock TCNT (overflow) FFFFh 0000h...
Page 399: Usage Notes
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.6 Usage Notes 19.6.1 Module Clock Stop Mode Setting MTU operation can be disabled or enabled using the module stop control register. MTU operation is stopped with the initial setting. Register access is enabled by releasing the module clock stop mode. For details, refer to section 11, Low Power Consumption .
Page 400: Contention Between Tcnt Write And Clear Operations
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.6.4 Contention between TCNT Write and Clear Operations If the counter clear signal is generated in a TCNT write cycle, the TCNT counter clearing takes precedence and the TCNT counter write operation is not performed. Figure 19.55 shows the timing in this case.
Page 401: Contention Between Tgr Write Operation And Compare Match
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.6.6 Contention between TGR Write Operation and Compare Match If a compare match occurs in a TGR write cycle, the TGR register write operation is executed and the compare match signal is also generated. Figure 19.57 shows the timing in this case.
Page 402: Contention Between Buffer Register Write And Tcnt Clear Operations
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.6.8 Contention between Buffer Register Write and TCNT Clear Operations When the buffer transfer timing is set at the TCNT clear timing by the timer buffer operation transfer mode register (TBTM), if TCNT clearing occurs in a TGR write cycle, the data before write operation is transferred to TGR by the buffer operation.
Page 403: Contention Between Tgr Write Operation And Input Capture
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.6.10 Contention between TGR Write Operation and Input Capture If an input capture signal is generated in a TGR write cycle, the input capture operation takes precedence and the TGR register write operation is not performed in MTU0 to MTU2. In MTU5, the TGR register write operation is performed and the input capture signal is generated.
Page 404: Contention Between Buffer Register Write Operation And Input Capture
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.6.11 Contention between Buffer Register Write Operation and Input Capture If an input capture signal is generated in a buffer register write cycle, the buffer operation takes precedence and the buffer register write operation is not performed.
Page 405: Contention Between Mtu2.Tcnt Write Operation And Overflow/Underflow In Cascaded Operation
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.6.12 Contention between MTU2.TCNT Write Operation and Overflow/Underflow in Cascaded Operation With timer counters MTU1.TCNT and MTU2.TCNT in a cascade, when a contention occurs between MTU1.TCNT counting (an MTU2.TCNT counter overflow/underflow) and the MTU2.TCNT write cycle, the MTU2.TCNT write operation is performed and the MTU1.TCNT count signal is disabled.
Page 406: Contention Between Overflow/Underflow And Counter Clearing
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.6.13 Contention between Overflow/Underflow and Counter Clearing If an overflow/underflow and counter clearing occur simultaneously, the TCNT counter clearing takes precedence and the corresponding TCIV interrupt is not generated. If an overflow and counter clearing due to an input capture occur simultaneously, an input capture interrupt signal is output and an overflow interrupt signal is not output.
Page 407: Interrupts During Periods In The Module Stop State
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.6.15 Interrupts during Periods in the Module Stop State When an module that has issued an interrupt request enters the module stop state, clearing the source of the interrupt for the CPU or activation signal for the DTC is not possible. Accordingly, disable interrupts, etc.
Page 408: Continuous Output Of Interrupt Signal In Response To A Compare Match
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.6.18 Continuous Output of Interrupt Signal in Response to a Compare Match When the TGR register is set to 0000h, PCLK/1 is set as the count clock, and compare match is set as the trigger for clearing of the count clock, the value of the TCNT counter remains 0000h, and the interrupt signal will be output continuously (i.e.
Page 409: Mtu Output Pin Initialization
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.7 MTU Output Pin Initialization 19.7.1 Operating Modes The MTU has the following four operating modes. Waveforms can be output in any of these modes.  Normal mode (MTU0 to MTU2) ...
Page 410: Overview Of Pin Initialization Procedures And Mode Transitions In Case Of Error During Operation
RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) 19.7.3 Overview of Pin Initialization Procedures and Mode Transitions in Case of Error during Operation  When making a transition to a mode (Normal, PWM1, PWM2, or PCM) in which the pin output level is selected by the TIOR register setting, initialize the pins by means of the TIOR register setting.
Page 411 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (1) Operation When Error Occurs in Normal Mode and Operation is Restarted in Normal Mode Figure 19.68 shows a case in which an error occurs in normal mode and operation is restarted in normal mode after re- setting.
Page 412 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (2) Operation When Error Occurs in Normal Mode and Operation is Restarted in PWM Mode 1 Figure 19.69 shows a case in which an error occurs in normal mode and operation is restarted in PWM mode 1 after re- setting.
Page 413 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (4) Operation When Error Occurs in Normal Mode and Operation is Restarted in Phase Counting Mode Figure 19.71 shows a case in which an error occurs in normal mode and operation is restarted in phase counting mode after re-setting.
Page 414 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (5) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Normal Mode Figure 19.72 shows a case in which an error occurs in PWM mode 1 and operation is restarted in normal mode after re- setting.
Page 415 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (6) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in PWM mode 1 Figure 19.73 shows a case in which an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re- setting.
Page 416 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (8) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Phase Counting Mode Figure 19.75 shows a case in which an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting.
Page 417 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (9) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in Normal Mode Figure 19.76 shows a case in which an error occurs in PWM mode 2 and operation is restarted in normal mode after re- setting.
Page 418 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (10) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in PWM Mode 1 Figure 19.77 shows a case in which an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re- setting.
Page 419 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (12) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in Phase Counting Mode Figure 19.79 shows a case in which an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting.
Page 420 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (13) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in Normal Mode Figure 19.80 shows a case in which an error occurs in phase counting mode and operation is restarted in normal mode after re-setting.
Page 421 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (14) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in PWM Mode 1 Figure 19.81 shows a case in which an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting.
Page 422 RX110 Group 19. Multi-Function Timer Pulse Unit 2 (MTU2b) (15) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in PWM Mode 2 Figure 19.82 shows a case in which an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting.
Page 423: Compare Match Timer (Cmt)
RX110 Group 20. Compare Match Timer (CMT) Compare Match Timer (CMT) This MCU has an on-chip compare match timer (CMT) unit (unit 0) consisting of a two-channel 16-bit timer (i.e., a total of two channels). The CMT has a 16-bit counter, and can generate interrupts at set intervals. In this section, “PCLK”...
Page 424: Register Descriptions
RX110 Group 20. Compare Match Timer (CMT) 20.2 Register Descriptions 20.2.1 Compare Match Timer Start Register 0 (CMSTR0) Address(es): 0008 8000h — — — — — — — — — — — — — — STR1 STR0 Value after reset: Symbol Bit Name Description...
Page 425: Compare Match Counter (Cmcnt)
RX110 Group 20. Compare Match Timer (CMT) 20.2.3 Compare Match Counter (CMCNT) Address(es): CMT0.CMCNT 0008 8004h, CMT1.CMCNT 0008 800Ah Value after reset: The CMCNT counter is a readable/writable up-counter. When an frequency dividing clock is selected by the CMCR.CKS[1:0] bits and the CMSTR0.STRn (n = 0, 1) bit is set to 1, the CMCNT counter starts counting up using the selected clock.
Page 426: Operation
RX110 Group 20. Compare Match Timer (CMT) 20.3 Operation 20.3.1 Periodic Count Operation When an frequency dividing clock is selected by the CMCR.CKS[1:0] bits and the CMSTR0.STRn (n = 0, 1) bit is set to 1, the CMCNT counter starts counting up using the selected clock. When the value in the counter and the value in the register match, a compare match interrupt (CMIn) (n = 0,1) is generated.
Page 427: Interrupts
RX110 Group 20. Compare Match Timer (CMT) 20.4 Interrupts 20.4.1 Interrupt Sources The CMT has channels and each of them to which a different vector address is allocated has a compare match interrupt (CMIn) (n = 0, 1). When a compare match interrupt occurs, the corresponding interrupt request is output. When the interrupt request is used to generate a CPU interrupt, the priority of channels can be changed by the interrupt controller settings.
Page 428: Usage Notes
RX110 Group 20. Compare Match Timer (CMT) 20.5 Usage Notes 20.5.1 Setting the Module Stop Function The CMT can be enabled or disabled using the module stop control register. After a reset, the CMT is in the module stop state. The registers can be accessed by releasing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 429: Realtime Clock (Rtca)
RX110 Group 21. Realtime Clock (RTCA) Realtime Clock (RTCA) In this section, “PCLK” is used to refer to PCLKB. 21.1 Overview The RTC has two types of counting modes: calendar count mode and binary count mode. They are used by switching the register settings.
Page 430 RX110 Group 21. Realtime Clock (RTCA) Internal peripheral bus Realtime clock (RTC) Bus interface To each RCR2 RTCOUT function Time counter 1-Hz/64-Hz output Alarm function Prescaler XCIN 128 Hz RSECAR/ RMINAR/ 32.768 kHz Sub-clock RSECCNT/ 128-Hz generation R64CNT BCNT0AR BCNT1AR BCNT0 for XCIN oscillator...
Page 431: Register Descriptions
RX110 Group 21. Realtime Clock (RTCA) 21.2 Register Descriptions When writing to or reading from RTC registers, do so in accordance with section 21.5.5, Notes When Writing to and Reading from Registers . If the value in an RTC register after a reset is given as x (undefined bits) in the list, it is not initialized by a reset. When RTC enters the reset state or a low power consumption state during counting operations (i.e.
Page 432: Second Counter (Rseccnt)/Binary Counter 0 (Bcnt0)
RX110 Group 21. Realtime Clock (RTCA) 21.2.2 Second Counter (RSECCNT)/Binary Counter 0 (BCNT0) (1) In calendar count mode: Address(es): RSECCNT 0008 C402h — SEC10[2:0] SEC1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 SEC1[3:0] 1-Second Count Counts from 0 to 9 every second.
Page 433: Minute Counter (Rmincnt)/Binary Counter 1 (Bcnt1)
RX110 Group 21. Realtime Clock (RTCA) 21.2.3 Minute Counter (RMINCNT)/Binary Counter 1 (BCNT1) (1) In calendar count mode: Address(es): RMINCNT 0008 C404h — MIN10[2:0] MIN1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 MIN1[3:0] 1-Minute Count Counts from 0 to 9 every minute.
Page 434: Hour Counter (Rhrcnt)/Binary Counter 2 (Bcnt2)
RX110 Group 21. Realtime Clock (RTCA) 21.2.4 Hour Counter (RHRCNT)/Binary Counter 2 (BCNT2) (1) In calendar count mode: Address(es): RHRCNT 0008 C406h — HR10[1:0] HR1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 HR1[3:0] 1-Hour Count Counts from 0 to 9 once per hour.
Page 435: Day-Of-Week Counter (Rwkcnt)/Binary Counter 3 (Bcnt3)
RX110 Group 21. Realtime Clock (RTCA) 21.2.5 Day-of-Week Counter (RWKCNT)/Binary Counter 3 (BCNT3) (1) In calendar count mode: Address(es): RWKCNT 0008 C408h — — — — — DAYW[2:0] Value after reset: x: Undefined Symbol Bit Name Description b2 to b0 DAYW[2:0] Day-of-Week Counting 0 0 0: Sunday...
Page 436: Date Counter (Rdaycnt)
RX110 Group 21. Realtime Clock (RTCA) 21.2.6 Date Counter (RDAYCNT) Address(es): 0008 C40Ah — — DATE10[1:0] DATE1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 DATE1[3:0] 1-Day Count Counts from 0 to 9 once per day. When a carry is generated, 1 is added to the tens place.
Page 437: Month Counter (Rmoncnt)
RX110 Group 21. Realtime Clock (RTCA) 21.2.7 Month Counter (RMONCNT) Address(es): 0008 C40Ch — — — MON10 MON1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 MON1[3:0] 1-Month Count Counts from 0 to 9 once per month. When a carry is generated, 1 is added to the tens place.
Page 438: Second Alarm Register (Rsecar)/Binary Counter 0 Alarm Register (Bcnt0Ar)
RX110 Group 21. Realtime Clock (RTCA) 21.2.9 Second Alarm Register (RSECAR)/Binary Counter 0 Alarm Register (BCNT0AR) (1) In calendar count mode: Address(es): RSECAR 0008 C410h SEC10[2:0] SEC1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 SEC1[3:0] 1 Second Value for the ones place of seconds b6 to b4...
Page 439: Minute Alarm Register (Rminar)/Binary Counter 1 Alarm Register (Bcnt1Ar)
RX110 Group 21. Realtime Clock (RTCA) 21.2.10 Minute Alarm Register (RMINAR)/Binary Counter 1 Alarm Register (BCNT1AR) (1) In calendar count mode: Address(es): RMINAR 0008 C412h MIN10[2:0] MIN1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 MIN1[3:0] 1 Minute Value for the ones place of minutes b6 to b4...
Page 440: Hour Alarm Register (Rhrar)/Binary Counter 2 Alarm Register (Bcnt2Ar)
RX110 Group 21. Realtime Clock (RTCA) 21.2.11 Hour Alarm Register (RHRAR)/Binary Counter 2 Alarm Register (BCNT2AR) (1) In calendar count mode: Address(es): RHRAR 0008 C414h HR10[1:0] HR1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 HR1[3:0] 1 Hour Value for the ones place of hours b5, b4...
Page 441: Day-Of-Week Alarm Register (Rwkar)/Binary Counter 3 Alarm Register (Bcnt3Ar)
RX110 Group 21. Realtime Clock (RTCA) 21.2.12 Day-of-Week Alarm Register (RWKAR)/Binary Counter 3 Alarm Register (BCNT3AR) (1) In calendar count mode: Address(es): RWKAR 0008 C416h — — — — DAYW[2:0] Value after reset: x: Undefined Symbol Bit Name Description b2 to b0 DAYW[2:0] Day-of-Week Setting 0 0 0: Sunday...
Page 442: Date Alarm Register (Rdayar)/Binary Counter 0 Alarm Enable Register (Bcnt0Aer)
RX110 Group 21. Realtime Clock (RTCA) 21.2.13 Date Alarm Register (RDAYAR)/Binary Counter 0 Alarm Enable Register (BCNT0AER) (1) In calendar count mode: Address(es): RDAYAR 0008 C418h — DATE10[1:0] DATE1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 DATE1[3:0] 1 Day Value for the ones place of days...
Page 443: Month Alarm Register (Rmonar)/Binary Counter 1 Alarm Enable Register (Bcnt1Aer)
RX110 Group 21. Realtime Clock (RTCA) 21.2.14 Month Alarm Register (RMONAR)/Binary Counter 1 Alarm Enable Register (BCNT1AER) (1) In calendar count mode: Address(es): RMONAR 0008 C41Ah — — MON10 MON1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 MON1[3:0] 1 Month Value for the ones place of months...
Page 444: Year Alarm Register (Ryrar)/Binary Counter 2 Alarm Enable Register (Bcnt2Aer)
RX110 Group 21. Realtime Clock (RTCA) 21.2.15 Year Alarm Register (RYRAR)/Binary Counter 2 Alarm Enable Register (BCNT2AER) (1) In calendar count mode: Address(es): RYRAR 0008 C41Ch — — — — — — — — YR10[3:0] YR1[3:0] Value after reset: x: Undefined Symbol Bit Name Description...
Page 445: Year Alarm Enable Register (Ryraren)/Binary Counter 3 Alarm Enable Register (Bcnt3Aer)
RX110 Group 21. Realtime Clock (RTCA) 21.2.16 Year Alarm Enable Register (RYRAREN)/Binary Counter 3 Alarm Enable Register (BCNT3AER) (1) In calendar count mode: Address(es): RYRAREN 0008 C41Eh — — — — — — — Value after reset: x: Undefined Symbol Bit Name Description b6 to b0...
Page 446: Rtc Control Register 1 (Rcr1)
RX110 Group 21. Realtime Clock (RTCA) 21.2.17 RTC Control Register 1 (RCR1) Address(es): 0008 C422h PES[3:0] RTCOS Value after reset: x: Undefined Symbol Bit Name Description Alarm Interrupt Enable 0: An alarm interrupt request is disabled. 1: An alarm interrupt request is enabled. Carry Interrupt Enable 0: A carry interrupt request is disabled.
Page 447: Rtc Control Register 2 (Rcr2)
RX110 Group 21. Realtime Clock (RTCA) 21.2.18 RTC Control Register 2 (RCR2) (1) In calendar count mode: Address(es): 0008 C424h CNTM HR24 AADJP AADJE RTCOE ADJ30 RESET START Value after reset: x: Undefined Symbol Bit Name Description START Start 0: Prescaler and time counter are stopped. 1: Prescaler and time counter operate normally.
Page 448 RX110 Group 21. Realtime Clock (RTCA) initialization is completed, the RESET bit is automatically set to 0. When 1 is written to the RESET bit, check that the bit is set to 0, and then make next settings. ADJ30 Bit (30-Second Adjustment) This bit is for 30-second adjustment.
Page 449 RX110 Group 21. Realtime Clock (RTCA) (2) In binary count mode: Address(es): 0008 C424h CNTM — AADJP AADJE RTCOE — RESET START Value after reset: x: Undefined Symbol Bit Name Description START Start 0: The 32-bit binary counter, 64-Hz counter, and prescaler are stopped.
Page 450 RX110 Group 21. Realtime Clock (RTCA) RTCOE Bit (RTCOUT Output Enable) This bit enables output of a 1-Hz/64-Hz clock signal from the RTCOUT pin. Use the START bit to stop counting by the counters before changing the value of the RTCOE bit. Do not stop counting (write 0 to the START bit) and change the value of the RTCOE bit at the same time.
Page 451: Rtc Control Register 3 (Rcr3)
RX110 Group 21. Realtime Clock (RTCA) 21.2.19 RTC Control Register 3 (RCR3) Address(es): 0008 C426h — — — — RTCDV[2:0] RTCEN Value after reset: x: Undefined Symbol Bit Name Description RTCEN Sub-Clock Oscillator Control 0: Sub-clock oscillator is stopped. 1: Sub-clock oscillator is operating. b3 to b1 RTCDV[2:0] Sub-Clock Oscillator Drive...
Page 452: Time Error Adjustment Register (Radj)
RX110 Group 21. Realtime Clock (RTCA) 21.2.20 Time Error Adjustment Register (RADJ) Address(es): 0008 C42Eh PMADJ[1:0] ADJ[5:0] Value after reset: x: Undefined Symbol Bit Name Description b5 to b0 ADJ[5:0] Adjustment Value These bits specify the adjustment value from the prescaler. b7, b6 PMADJ[1:0] Plus–Minus...
Page 453: Operation
RX110 Group 21. Realtime Clock (RTCA) 21.3 Operation 21.3.1 Outline of Initial Settings of Registers after Power On After the power is turned on, the initial settings for the clock setting, count mode setting, time error adjustment, time setting, alarm, and interrupt should be performed. Power on Clock supply setting and count mode setting Clock and count mode settings...
Page 454: Clock And Count Mode Setting Procedure
RX110 Group 21. Realtime Clock (RTCA) 21.3.2 Clock and Count Mode Setting Procedure Figure 21.3 shows how to set the clock and the count mode. Set the sub-clock oscillator Set the RCR3 register Supply 6 clocks of the count source Set the START bit to 0 Wait for the RCR2.START bit to become 0 START = 0...
Page 455: Setting The Time
RX110 Group 21. Realtime Clock (RTCA) 21.3.3 Setting the Time Figure 21.4 shows how to set the time. Set the START bit to 0 Write 0 to the RCR2.START bit Wait for the RCR2.START bit to become 0 START = 0 Execute an RTC software reset Write 1 to the RCR2.RESET bit* Wait for the RCR2.RESET bit to become 0...
Page 456: Reading 64-Hz Counter And Time
RX110 Group 21. Realtime Clock (RTCA) 21.3.5 Reading 64-Hz Counter and Time Figure 21.6 shows how to read the 64-Hz counter and time. (a) To read the time without using interrupt Disable the ICU carry interrupt request Write 0 to the interrupt request enable bit corresponding to the CUP interrupt Enable the RTC carry interrupt request Write 1 to the RCR1.CIE bit...
Page 457: Alarm Function
RX110 Group 21. Realtime Clock (RTCA) 21.3.6 Alarm Function Figure 21.7 shows how to use the alarm function. Check that the count is in operation Clock running (the RCR2.START bit is 1) Write 0 to the interrupt request enable bit Disable the ICU alarm interrupt request corresponding to the ALM interrupt Set alarm enable at the same time as or after the...
Page 458: Procedure For Disabling Alarm Interrupt
RX110 Group 21. Realtime Clock (RTCA) 21.3.7 Procedure for Disabling Alarm Interrupt Figure 21.8 shows the procedure for disabling the enabled alarm interrupt request. Enable the alarm interrupt The RCR1.AIE bit register has been set to 1 Write 0 to the interrupt request enable bit Disable the alarm interrupt request of corresponding to the ALM interrupt the ICU...
Page 459: Adjustment By Software
RX110 Group 21. Realtime Clock (RTCA) Register settings: (when RCR2.CNTMD = 0)  RCR2.AADJP = 0 (adjustment every minute)  RADJ.PMADJ[1:0] = 10b (adjustment is performed by the subtraction from the prescaler.)  RADJ.ADJ[5:0] = 60 (3Ch) [Example 2] Sub-clock running at 32.766 kHz Adjustment procedure: When the sub-clock is running at 32.766 kHz, 1 second elapses every 32,766 clock cycles.
Page 460: Procedure For Changing The Mode Of Adjustment
RX110 Group 21. Realtime Clock (RTCA) 21.3.8.3 Procedure for Changing the Mode of Adjustment When changing the mode of adjustment, change the value of the AADJE bit in RCR2 after setting the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed). Changing from adjustment by software to automatic adjustment: Set the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
Page 461: Interrupt Sources
RX110 Group 21. Realtime Clock (RTCA) 21.4 Interrupt Sources There are three interrupt sources in the realtime clock. Table 21.3 lists interrupt sources for the RTC. Table 21.3 RTC Interrupt Sources Name Interrupt Sources Alarm interrupt Periodic interrupt Carry interrupt (1) Alarm interrupt (ALM) This interrupt is generated according to the result of comparison between the alarm registers and realtime clock counters (for details, refer to section 21.3.6, Alarm Function ).
Page 462 RX110 Group 21. Realtime Clock (RTCA) (3) Carry interrupt (CUP) This interrupt is generated when a carry to the second counter/binary counter 0 occurred or a carry to the R64CNT counter occurred during read access to the 64-Hz counter. 64 Hz Interrupt generated by the simultaneous R64CNT occurrence of the selected edge of the...
Page 463: Usage Notes
RX110 Group 21. Realtime Clock (RTCA) 21.5 Usage Notes 21.5.1 Register Writing during Counting The following registers should not be written to during counting (while the RCR2.START bit = 1). RSECCNT/BCNT0, RMINCNT/BCNT1, RHRCNT/BCNT2, RDAYCNT, RWKCNT/BCNT3, RMONCNT, RYRCNT, RCR1.RTCOS, RCR2.RTCOE, RCR2.HR24 The counter must be stopped before writing to any of the above registers.
Page 464: Transitions To Low Power Consumption Modes After Setting Registers
RX110 Group 21. Realtime Clock (RTCA) 21.5.4 Transitions to Low Power Consumption Modes after Setting Registers A transition to a low power consumption state (software standby mode) during writing to or updating of an RTC register might destroy the register’s value. After setting a register, confirm that the setting is in place before initiating a transition to a low power consumption state.
Page 465: Initialization Procedure When The Realtime Clock Is Not To Be Used
RX110 Group 21. Realtime Clock (RTCA) 21.5.7 Initialization Procedure When the Realtime Clock is Not to be Used Registers in the RTC are not initialized by a reset. Accordingly, depending on the initial state, the generation of an unintentional interrupt request or operation of the counter may lead to increased power consumption. For products that do not require a realtime clock, initialize the registers by following the initialization procedure shown in Figure 21.12 .
Page 466: Independent Watchdog Timer (Iwdta)
RX110 Group 22. Independent Watchdog Timer (IWDTa) Independent Watchdog Timer (IWDTa) In this section, “PCLK” is used to refer to PCLKB. 22.1 Overview The independent watchdog timer (IWDT) can be used to detect programs being out of control. The user can detect when a program runs out of control if an underflow occurs, by creating a program that refreshes the IWDT counter before it underflows.
Page 467 RX110 Group 22. Independent Watchdog Timer (IWDTa) To use the IWDT, the IWDT-dedicated clock (IWDTCLK) should be supplied so that the IWDT operates even if the peripheral module clock (PCLK) stops. The bus interface and registers operate with PCLK, and the 14-bit counter and control circuits operate with IWDTCLK.
Page 468: Register Descriptions
RX110 Group 22. Independent Watchdog Timer (IWDTa) 22.2 Register Descriptions 22.2.1 IWDT Refresh Register (IWDTRR) Address(es): IWDT.IWDTRR 0008 8030h Value after reset: Description b7 to b0 The counter is refreshed by writing 00h and then writing FFh to this register. The IWDTRR register refreshes the counter of the IWDT.
Page 469: Iwdt Control Register (Iwdtcr)
RX110 Group 22. Independent Watchdog Timer (IWDTa) 22.2.2 IWDT Control Register (IWDTCR) Address(es): IWDT.IWDTCR 0008 8032h — — RPSS[1:0] — — RPES[1:0] CKS[3:0] — — TOPS[1:0] Value after reset: Symbol Bit Name Description b1, b0 TOPS[1:0] Timeout Period Select b1 b0 0 0: 128 cycles (007Fh) 0 1: 512 cycles (01FFh) 1 0: 1024 cycles (03FFh)
Page 470 RX110 Group 22. Independent Watchdog Timer (IWDTa) TOPS[1:0] Bits (Timeout Period Select) These bits select the timeout period (period until the counter underflows) from among 128, 512, 1024, or 2048 cycles, taking the divided clock specified by the CKS[3:0] bits as one cycle. After the counter is refreshed, the combination of the CKS[3:0] and TOPS[1:0] bits determines the time (number of IWDTCLK cycles) until the counter underflows.
Page 471 RX110 Group 22. Independent Watchdog Timer (IWDTa) RPES[1:0] Bits (Window End Position Select) These bits select 75%, 50%, 25% or 0% of the count period for the window end position of the counter. The window end position should be a value smaller than the window start position (window start position > window end position). If the window end position is greater than the window start position, only the window start position setting is enabled.
Page 472: Iwdt Status Register (Iwdtsr)
RX110 Group 22. Independent Watchdog Timer (IWDTa) 22.2.3 IWDT Status Register (IWDTSR) Address(es): IWDT.IWDTSR 0008 8034h REFEF UNDFF CNTVAL[13:0] Value after reset: Symbol Bit Name Description b13 to b0 CNTVAL[13:0] Counter Value Value counted by the counter UNDFF Underflow Flag 0: No underflow occurred R/(W) 1: Underflow occurred...
Page 473: Iwdt Reset Control Register (Iwdtrcr)
RX110 Group 22. Independent Watchdog Timer (IWDTa) 22.2.4 IWDT Reset Control Register (IWDTRCR) Address(es): IWDT.IWDTRCR 0008 8036h RSTIR — — — — — — — Value after reset: Symbol Bit Name Description b6 to b0 — Reserved These bits are read as 0. Writing to these bits has no effect. RSTIRQS Reset Interrupt Request Select 0: Non-maskable interrupt request output is enabled.
Page 474: Iwdt Count Stop Control Register (Iwdtcstpr)
RX110 Group 22. Independent Watchdog Timer (IWDTa) 22.2.5 IWDT Count Stop Control Register (IWDTCSTPR) Address(es): IWDT.IWDTCSTPR 0008 8038h SLCST — — — — — — — Value after reset: Symbol Bit Name Description b6 to b0 — Reserved These bits are read as 0. Writing to these bits has no effect. SLCSTP Sleep Mode Count Stop Control 0: Count stop is disabled.
Page 475: Operation
RX110 Group 22. Independent Watchdog Timer (IWDTa) 22.3 Operation 22.3.1 Count Operation in Each Start Mode Select the IWDT start mode by setting the IWDT start mode select bit (OFS0.IWDTSTRT) in option function select register 0. When the OFS0.IWDTSTRT bit is 1 (register start mode), the IWDT control register (IWDTCR), IWDT reset control register (IWDTRCR), and IWDT count stop control register (IWDTCSTPR) are enabled, and counting is started by refreshing (writing) the IWDT refresh register (IWDTRR).
Page 476 RX110 Group 22. Independent Watchdog Timer (IWDTa) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES# pin IWDT Control register (IWDTCR) (1) Initial value Writing to the Writing to the Writing to the (2) Set value register is invalid.
Page 477: Auto-Start Mode
RX110 Group 22. Independent Watchdog Timer (IWDTa) 22.3.1.2 Auto-Start Mode When the IWDT start mode select bit (OFS0.IWDTSTRT) in option function select register 0 is 0, auto-start mode is selected, and the IWDT control register (IWDTCR), IWDT reset control register (IWDTRCR), and IWDT count stop control register (IWDTCSTPR) are disabled.
Page 478 RX110 Group 22. Independent Watchdog Timer (IWDTa) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES# pin Refresh the counter Active: High Counting starts Counting starts Counting starts Counting starts Underflow Refresh error Refresh error Status flag Refresh error flag cleared Active: High...
Page 479: Control Over Writing To The Iwdtcr, Iwdtrcr, And Iwdtcstpr Registers
RX110 Group 22. Independent Watchdog Timer (IWDTa) 22.3.2 Control over Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers Writing to the IWDT control register (IWDTCR), IWDT reset control register (IWDTRCR), or IWDT count stop control register (IWDTCSTPR) is only possible once between the release from the reset state and the first refresh operation. After a refresh operation (counting starts) or the IWDTCR, IWDTRCR, or IWDTCSTPR register is written to, the protection signal in the IWDT becomes 1 to protect registers IWDTCR, IWDTRCR, and IWDTCSTPR against subsequent attempts at writing.
Page 480: Refresh Operation
RX110 Group 22. Independent Watchdog Timer (IWDTa) 22.3.3 Refresh Operation The counter is refreshed and starts operation (counting is started by refreshing) by writing the values 00h and then FFh to the IWDT refresh register (IWDTRR). If a value other than FFh is written after 00h, the counter is not refreshed. After such invalid writing, correct refreshing is performed by again writing 00h and then FFh to the IWDT refresh register (IWDTRR).
Page 481 RX110 Group 22. Independent Watchdog Timer (IWDTa) Figure 22.6 shows the IWDT refresh-operation waveforms when PCLK > IWDTCLK and clock divide ratio = IWDTCLK. Peripheral module clock (PCLK) IWDT-dedicated clock (IWDTCLK) Data written to IWDTRR register IWDTRR register write Valid signal (internal signal) IWDTRR register Invalid...
Page 482: Status Flags
RX110 Group 22. Independent Watchdog Timer (IWDTa) 22.3.4 Status Flags The refresh error (IWDTSR.REFEF) and underflow (IWDTSR.UNDFF) flags retain the source of the reset signal output from the IWDT or the source of the interrupt request from the IWDT. Thus, after release from the reset state or interrupt request generation, read the IWDTSR.REFEF and IWDTSR.UNDFF flags to check for the reset or interrupt source.
Page 483: Reading The Counter Value
RX110 Group 22. Independent Watchdog Timer (IWDTa) 22.3.7 Reading the Counter Value As the counter in IWDT-dedicated clock (IWDTCLK), the counter value cannot be read directly. The IWDT synchronizes the counter value with the peripheral module clock (PCLK) and stores it in the counter value bits (IWDTSR.CNTVAL[13:0]) of the IWDT status register.
Page 484: Correspondence Between Option Function Select Register 0 (Ofs0) And Iwdt Registers
RX110 Group 22. Independent Watchdog Timer (IWDTa) 22.3.8 Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers Table 22.5 lists the correspondence between option function select register 0 (OFS0) used in auto-start mode and the registers used in register start mode. Do not change the OFS0 register setting during IWDT operation.
Page 485: Serial Communications Interface (Scie, Scif)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Serial Communications Interface (SCIe, SCIf) This MCU has three independent serial communications interface (SCI) channels. The SCI consists of the SCIe module (SCI1 and SCI5) and the SCIf module (SCI12). The SCIe module (SCI1 and SCI5) can handle both asynchronous and clock synchronous serial communications. Asynchronous serial data communications can be carried out with standard asynchronous communications chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communications Interface Adapter (ACIA).
Page 486 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Table 23.1 SCIe Specifications (2/2) Item Description Clock synchronous Data length 8 bits mode Receive error detection Overrun error Hardware flow control CTSn# and RTSn# pins can be used in controlling transmission/reception. Smart card interface Error processing An error signal can be automatically transmitted when detecting a parity error during...
Page 487 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Table 23.2 SCIf Specifications (2/2) Item Description Clock Data length 8 bits synchronous Receive error detection Overrun error mode Hardware flow control CTSn# and RTSn# pins can be used in controlling transmission/reception. Smart card Error processing An error signal can be automatically transmitted when detecting a parity error during...
Page 488 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Module data bus SCMR PCLK RXDn/ Baud rate SSCLn/ PCLK/4 generator SMISOn SEMR PCLK/16 SNFR TXDn/ PCLK/64 SIMR1 SSDAn/ SMOSIn SIMR2 RTSn#/ SIMR3 CTSn#/ SISR SSn# MTIOC1A SPMR Parity addition MTIOC2A Transmission Clock Parity check and reception...
Page 489 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) SCK12 RTS12#/CTS12#/SS12# MTIOC1A MTIOC2A Extended serial mode control section RXD12/SSCL12/ SCIe SMISO12/RXDX12 TXD12/SSDA12/ SMOSI12/TXDX12/ SIOX12 SCIX0 interrupt request SCIX1 interrupt request Controller SCIX2 interrupt request SCIX3 interrupt request Timer unit RXI interrupt request TXI interrupt request TEI interrupt request ERI interrupt request...
Page 490 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Table 23.4 to Table 23.7 list the pin configuration of the SCIs for the individual modes. Table 23.4 SCI Pin Configuration in Asynchronous Mode and Clock Synchronous Mode Channel Pin Name Function SCI1 SCK1 SCI1 clock input/output...
Page 491: Register Descriptions
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2 Register Descriptions 23.2.1 Receive Shift Register (RSR) RSR is a shift register which is used to receive serial data input from the RXDn pin and converts it into parallel data. When one frame of data has been received, it is automatically transferred to the RDR register. The RSR register cannot be directly accessed by the CPU.
Page 492: Serial Mode Register (Smr)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.5 Serial Mode Register (SMR) Note: Some bits in SMR have different functions in smart card interface mode and non-smart card interface mode. (1) Non-Smart Card Interface Mode (SCMR.SMIF = 0) Address(es): SCI1.SMR 0008 A020h, SCI5.SMR 0008 A0A0h, SCI12.SMR 0008 B300h STOP CKS[1:0] Value after reset:...
Page 493 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) PM Bit (Parity Mode) Selects the parity mode (even or odd) for transmission and reception. The setting of the PM bit is invalid in multi-processor mode. PE Bit (Parity Enable) When this bit is set to 1, the parity bit is added to transmit data, and the parity bit is checked in reception. Irrespective of the setting of the PE bit, the parity bit is not added or checked in multi-processor format.
Page 494 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) (2) Smart Card Interface Mode (SCMR.SMIF = 1) Address(es): SMCI1.SMR 0008 A020h, SMCI5.SMR 0008 A0A0h, SMCI12.SMR 0008 B300h BCP[1:0] CKS[1:0] Value after reset: Symbol Bit Name Description b1, b0 CKS[1:0] Clock Select b1 b0 R/W* 0 0: PCLK (n = 0)*...
Page 495 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) PM Bit (Parity Mode) Selects the parity mode for transmission and reception (even or odd). For details on the usage of this bit in smart card interface mode, refer to section 23.6.2, Data Format (Except in Block Transfer Mode) .
Page 496: Serial Control Register (Scr)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.6 Serial Control Register (SCR) Note: Some bits in the SCR register have different functions in smart card interface mode and non-smart card interface mode. (1) Non-Smart Card Interface Mode (SCMR.SMIF = 0) Address(es): SCI1.SCR 0008 A022h, SCI5.SCR 0008 A0A2h, SCI12.SCR 0008 B302h MPIE TEIE...
Page 497 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) CKE[1:0] Bits (Clock Enable) These bits select the clock source and SCKn pin function. The combination of the settings of these bits and of the SEMR.ACS0 bit sets the internal MTU clock. TEIE Bit (Transmit End Interrupt Enable) Enables or disables a TEI interrupt request.
Page 498 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) (2) Smart Card Interface Mode (SCMR.SMIF = 1) Address(es): SMCI1.SCR 0008 A022h, SMCI5.SCR 0008 A0A2h, SMCI12.SCR 0008 B302h MPIE TEIE CKE[1:0] Value after reset: Symbol Bit Name Description  When SMR.GM = 0 b1, b0 CKE[1:0] Clock Enable...
Page 499 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) RE Bit (Receive Enable) Enables or disables serial reception. When this bit is set to 1, serial reception is started by detecting the start bit. Note that the SMR register should be set prior to setting the RE bit to 1 in order to designate the reception format.
Page 500: Serial Status Register (Ssr)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.7 Serial Status Register (SSR) Some bits in the SSR register have different functions in smart card interface mode and non-smart card interface mode. (1) Non-Smart Card Interface Mode (SCMR.SMIF = 0) Address(es): SCI1.SSR 0008 A024h, SCI5.SSR 0008 A0A4h, SCI12.SSR 0008 B304h TDRE RDRF ORER...
Page 501 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) PER Flag (Parity Error Flag) Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition]  When a parity error is detected during reception Although receive data when the parity error occurs is transferred to RDR, no RXI interrupt request occurs.
Page 502 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) TDRE Flag (Transmit Data Empty Flag) Indicates whether the TDR register has data to be transmitted. [Setting condition]  When data is transferred from TDR to TSR [Clearing condition]  When data is written to TDR R01UH0421EJ0120 Rev.1.20 Page 502 of 968 Jul 29, 2016...
Page 503 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) (2) Smart Card Interface Mode (SCMR.SMIF = 1) Address(es): SMCI1.SSR 0008 A024h, SMCI5.SSR 0008 A0A4h, SMCI12.SSR 0008 B304h TDRE RDRF ORER TEND MPBT Value after reset: Symbol Bit Name Description MPBT Multi-Processor Bit Transfer This bit should be set to 0 in smart card interface mode.
Page 504 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) PER Flag (Parity Error Flag) Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition]  When a parity error is detected during reception Although receive data when the parity error occurs is transferred to RDR, no RXI interrupt request occurs.
Page 505: Smart Card Mode Register (Scmr)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.8 Smart Card Mode Register (SCMR) Address(es): SMCI1.SCMR 0008 A026h, SMCI5.SCMR 0008 A0A6h, SMCI12.SCMR 0008 B306h BCP2 — — — SDIR SINV — SMIF Value after reset: Symbol Bit Name Description SMIF Smart Card Interface Mode 0: Non-smart card interface mode R/W*...
Page 506 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) BCP2 Bit (Base Clock Pulse 2) Selects the number of base clock cycles in a 1-bit data transfer time in smart card interface mode. Set this bit in combination with the SMR.BCP[1:0] bits. Table 23.9 Combinations of the SCMR.BCP2 Bit and SMR.BCP[1:0] Bits SCMR.BCP2 Bit...
Page 507: Bit Rate Register (Brr)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.9 Bit Rate Register (BRR) Address(es): SCI1.BRR 0008 A021h, SCI5.BRR 0008 A0A1h, SCI12.BRR 0008 B301h Value after reset: The BRR register is an 8-bit register that adjusts the bit rate. As each SCI channel has independent baud rate generator control, different bit rates can be set for each. Table 23.10 shows the relationship between the setting (N) in the BRR register and the bit rate (B) for normal asynchronous mode, multi-processor transfer, clock synchronous mode, smart card interface mode, simple SPI mode, and simple I C mode.
Page 508 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Table 23.12 Clock Source Settings SMR.CKS[1:0] Bit Setting Clock Source PCLK PCLK/4 PCLK/16 PCLK/64 Table 23.13 Base Clock Settings in Smart Card Interface Mode SCMR.BCP2 Bit Setting SMR.BCP[1:0] Bit Setting Base Clock Cycles for 1-bit Period 93 clock cycles 128 clock cycles 186 clock cycles...
Page 509 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Table 23.14 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency PCLK (MHz) 9.8304 12.288 Bit Rate (bps) Error (%) n Error (%) Error (%) n Error (%) n Error (%) 0.03 –0.26...
Page 510 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Table 23.15 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) PCLK Maximum Bit Rate PCLK Maximum Bit Rate (MHz) (bps) (MHz) (bps) 250000 17.2032 537600 9.8304 307200 562500 312500 19.6608 614400 375000 625000 12.288...
Page 511 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Table 23.18 BRR Settings for Various Bit Rates (Clock Synchronous Mode, Simple SPI Mode) Operating Frequency PCLK (MHz) Bit Rate (bps) — — — — — — — — — — 2.5 k 10 k 25 k 50 k...
Page 512 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Table 23.20 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) Bit Rate (bps) PCLK (MHz) Error (%) 9600 7.1424 0.00 10.00 10.7136 13.00 8.99 14.2848 0.00 16.00...
Page 513 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Table 23.22 BRR Settings for Various Bit Rates (Simple I C Mode) Operating Frequency PCLK (MHz) Bit Rate (bps) Error (%) n Error (%) Error (%) n Error (%) n Error (%) 10 k –2.3 –3.8...
Page 514: Serial Extended Mode Register (Semr)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.10 Serial Extended Mode Register (SEMR) Address(es): SCI1.SEMR 0008 A027h, SCI5.SEMR 0008 A0A7h, SCI12.SEMR 0008 B307h RXDES — NFEN ABCS — — — ACS0 Value after reset: Symbol Bit Name Description ACS0 Asynchronous Mode (Valid only in asynchronous mode) R/W*...
Page 515 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) This figure shows an example when MTU clock is input to SCIn (n = 5, 12). MTU1, MTU2 SCI1 When generating 187.5 kbps of MTU average transfer rate for PCLK = 32 MHz: Base clock MTIOC1A (1) Generate a frequency of 4 MHz using MTIOC1A as the base clock.
Page 516: Noise Filter Setting Register (Snfr)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.11 Noise Filter Setting Register (SNFR) Address(es): SCI1.SNFR 0008 A028h, SCI5.SNFR 0008 A0A8h, SCI12.SNFR 0008 B308h — — — — — NFCS[2:0] Value after reset: Symbol Bit Name Description b2 to b0 NFCS[2:0] Noise Filter Clock Select In asynchronous mode, the standard setting for the base clock is as...
Page 517: I C Mode Register 1 (Simr1)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.12 C Mode Register 1 (SIMR1) Address(es): SCI1.SIMR1 0008 A029h, SCI5.SIMR1 0008 A0A9h, SCI12.SIMR1 0008 B309h IICDL[4:0] — — IICM Value after reset: Symbol Bit Name Description IICM Simple I C Mode Select SMIF IICM R/W* 0: Asynchronous mode, Multi-processor mode,...
Page 518: I 2 C Mode Register 2 (Simr2)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.13 C Mode Register 2 (SIMR2) Address(es): SCI1.SIMR2 0008 A02Ah, SCI5.SIMR2 0008 A0AAh, SCI12.SIMR2 0008 B30Ah IICACK IICCSC IICINT — — — — — Value after reset: Symbol Bit Name Description IICINTM C Interrupt Mode Select 0: Use ACK/NACK interrupts.
Page 519: I 2 C Mode Register 3 (Simr3)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.14 C Mode Register 3 (SIMR3) Address(es): SCI1.SIMR3 0008 A02Bh, SCI5.SIMR3 0008 A0ABh, SCI12.SIMR3 0008 B30Bh IICSTIF IICSTP IICRST IICSTA IICSCLS[1:0] IICSDAS[1:0] AREQ Value after reset: Symbol Bit Name Description IICSTAREQ Start Condition Generation 0: A start condition is not generated.
Page 520 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) IICSTPREQ Bit (Stop Condition Generation) When a stop condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b as well as setting the IICSTPREQ bit to 1. [Setting condition] ...
Page 521: I C Status Register (Sisr)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.15 C Status Register (SISR) Address(es): SCI1.SISR 0008 A02Ch, SCI5.SISR 0008 A0ACh, SCI12.SISR 0008 B30Ch IICACK — — — — — — — Value after reset: x: Undefined Symbol Bit Name Description IICACKR ACK Reception Data Flag 0: ACK received...
Page 522: Spi Mode Register (Spmr)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.16 SPI Mode Register (SPMR) Address(es): SCI1.SPMR 0008 A02Dh, SCI5.SPMR 0008 A0ADh, SCI12.SPMR 0008 B30Dh CKPH CKPOL — — CTSE Value after reset: Symbol Bit Name Description SSn# Pin Function Enable 0: SSn# pin function is disabled. R/W* 1: SSn# pin function is enabled.
Page 523: Extended Serial Module Enable Register (Esmer)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) MFF Flag (Mode Fault Flag) This bit indicates mode fault errors. In a multi-master configuration, determine the mode fault error occurrence by reading the MFF flag. [Setting condition]  Input on the SSn# pin being at the low level during master operation in simple SPI mode (SSE bit = 1 and MSS bit = 0) [Clearing condition] ...
Page 524: Control Register 0 (Cr0)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.18 Control Register 0 (CR0) Address(es): SCI12.CR0 0008 B321h — — — — BRME RXDSF SFSF — Value after reset: Symbol Bit Name Description — Reserved This bit is read as 0. The write value should be 0. SFSF Start Frame Status Flag 0: Start Frame detection function is disabled.
Page 525: Control Register 2 (Cr2)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.20 Control Register 2 (CR2) Address(es): SCI12.CR2 0008 B323h RTS[1:0] BCCS[1:0] — DFCS[2:0] Value after reset: Symbol Bit Name Description b2 to b0 DFCS[2:0] RXDX12 Signal Digital Filter 0 0 0: Filter is disabled. Clock Select 0 0 1: Filter clock is SCI base clock* 0 1 0: Filter clock is PCLK/8...
Page 526: Control Register 3 (Cr3)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.21 Control Register 3 (CR3) Address(es): SCI12.CR3 0008 B324h — — — — — — — SDST Value after reset: Symbol Bit Name Description SDST Start Frame Detection Start 0: Detection of Start Frame is not performed. 1: Detection of Start Frame is performed.
Page 527: Interrupt Control Register (Icr)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.23 Interrupt Control Register (ICR) Address(es): SCI12.ICR 0008 B326h AEDIE BCDIE PIBDIE CF1MI CF0MI — — BFDIE Value after reset: Symbol Bit Name Description BFDIE Break Field Low Width Detected 0: Interrupts on detection of the low width for a Break Field Interrupt Enable are disabled.
Page 528: Status Register (Str)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.24 Status Register (STR) Address(es): SCI12.STR 0008 B327h — — AEDF BCDF PIBDF CF1MF CF0MF BFDF Value after reset: Symbol Bit Name Description BFDF Break Field Low Width [Setting conditions]  Detection of the low width for a Break Field Detection Flag ...
Page 529: Status Clear Register (Stcr)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.25 Status Clear Register (STCR) Address(es): SCI12.STCR 0008 B328h AEDCL BCDCL PIBDC CF1MC CF0MC — — BFDCL Value after reset: Symbol Bit Name Description BFDCL BFDF Clear Setting this bit to 1 clears the STR.BFDF flag. This bit is read as 0. CF0MCL CF0MF Clear Setting this bit to 1 clears the STR.CF0MF flag.
Page 530: Control Field 0 Compare Enable Register (Cf0Cr)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.27 Control Field 0 Compare Enable Register (CF0CR) Address(es): SCI12.CF0CR 0008 B32Ah CF0CE CF0CE CF0CE CF0CE CF0CE CF0CE CF0CE CF0CE Value after reset: Symbol Bit Name Description CF0CE0 Control Field 0 Bit 0 Compare Enable 0: Comparison with bit 0 of Control Field 0 is disabled.
Page 531: Secondary Control Field 1 Data Register (Scf1Dr)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.30 Secondary Control Field 1 Data Register (SCF1DR) Address(es): SCI12.SCF1DR 0008 B32Dh Value after reset: PCF1DR is an 8-bit readable and writable register that holds the 8-bit secondary value for comparison with Control Field 23.2.31 Control Field 1 Compare Enable Register (CF1CR) Address(es): SCI12.CF1CR 0008 B32Eh...
Page 532: Timer Control Register (Tcr)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.33 Timer Control Register (TCR) Address(es): SCI12.TCR 0008 B330h — — — — — — — TCST Value after reset: Symbol Bit Name Description TCST Timer Count Start 0: Stops the timer counting 1: Starts the timer counting b7 to b1 —...
Page 533: Timer Prescaler Register (Tpre)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.2.35 Timer Prescaler Register (TPRE) Address(es): SCI12.TPRE 0008 B332h Value after reset: TPRE consists of an 8-bit reload register, a read buffer, and a counter, each of which has FFh as its initial value. The counter counts down in synchronization with the counter clock selected by the TMR.TCSS[2:0] bits, and is reloaded with the value in the reload register when it underflows.
Page 534: Operation In Asynchronous Mode
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.3 Operation in Asynchronous Mode Figure 23.4 shows the general format for asynchronous serial communications. One frame consists of a start bit (low level), transmit/receive data, a parity bit, and stop bits (high level). In asynchronous serial communications, the communications line is usually held in the mark state (high level).
Page 535: Serial Data Transfer Format
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.3.1 Serial Data Transfer Format Table 23.26 lists the serial data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details of multi-processor function, refer to section 23.4, Multi-Processor Communications Function .
Page 536: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.3.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times * the bit rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Since receive data is sampled at the rising edge of the 8th pulse * of the base clock, data is latched at the middle of each bit, as shown in Figure 23.5 .
Page 537: Clock
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.3.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCKn pin can be selected as the SCI’s transfer clock, according to the setting of the CM bit in the SMR register and the CKE[1:0] bits in the SCR register.
Page 538: Sci Initialization (Asynchronous Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.3.5 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, start by writing the initial value 00h to the SCR register and then continue through the procedure for SCI given in Figure 23.7 . Whenever the operating mode or transfer format is changed, the SCR register must be initialized before the change is made.
Page 539: Serial Data Transmission (Asynchronous Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.3.6 Serial Data Transmission (Asynchronous Mode) Figure 23.8 to Figure 23.10 show an example of the operation for serial transmission in asynchronous mode. In serial transmission, the SCI operates as described below. 1.
Page 540 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) CTSn# pin Data Start bit Parity bit Stop bit D7 0/1 1 D7 0/1 Idle state 0 D0 D1 0 D0 (mark state) SCR.TE bit 1 frame TXI interrupt flag (IRn in ICU SSR.TEND flag TXI interrupt request Data written to TDR in TXI...
Page 541 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Initialization [ 1 ] [ 1 ] SCI initialization: Set data transmission. After the TE bit in SCR is set to 1, 1 is output for a Start data transmission frame, and transmission is enabled. [ 2 ] Transmit data write to TDR by a TXI interrupt request: When transmit data is transferred from TDR to TSR, a...
Page 542: Serial Data Reception (Asynchronous Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.3.7 Serial Data Reception (Asynchronous Mode) Figure 23.12 and Figure 23.13 show an example of the operation for serial data reception in asynchronous mode. In serial data reception, the SCI operates as described below. 1.
Page 543 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Data Data Data Parity Stop Parity Stop Start bit Start bit Start bit Idle state (mark state) RXI interrupt flag (IRn in ICU* SSR.FER flag RDR data read in RXI interrupt RXI interrupt handling routine request generated...
Page 544 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) [ 1 ] Initialization [ 1 ] SCI initialization: Start data reception Set data reception. [ 2 ] [ 3 ] Receive error processing and break detection: [ 2 ] Read ORER, PER, and FER flags in SSR If a receive error occurs, an ERI interrupt is generated.
Page 545 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) [ 3 ] Error processing SSR.ORER flag = 1 Overrun error processing* [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR. In combination with step [ 7 ], this will make correct reception of the next frame possible.
Page 546: Multi-Processor Communications Function
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.4 Multi-Processor Communications Function Using the multi-processor communication functions enables to transmit and receive data by sharing a communication line between multiple processors by using asynchronous serial communication in which the multi-processor bit is added. In multi-processor communication, a unique ID code is allocated to each receiving station.
Page 547: Multi-Processor Serial Data Transmission
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.4.1 Multi-Processor Serial Data Transmission Figure 23.17 is a sample flowchart of multi-processor data transmission. In the ID transmission cycle, the ID should be transmitted with the SSR.MPBT bit set to 1. In the data transmission cycle, the data should be transmitted with the MPBT bit set to 0.
Page 548: Multi-Processor Serial Data Reception
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.4.2 Multi-Processor Serial Data Reception Figure 23.19 and Figure 23.20 are sample flowcharts of multi-processor data reception. When the SCR.MPIE bit is set to 1, reading the communication data is skipped until reception of the communication data in which the multi-processor bit is set to 1.
Page 549 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Initialization [ 1 ] [ 1 ] SCI initialization: Set data reception. Start data reception [ 2 ] ID reception cycle: Set the MPIE bit in SCR to 1 and wait for ID reception.
Page 550 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) [ 5 ] Error processing SSR.ORER flag = 1 Overrun error processing* [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR. In combination with step [ 7 ], this will make correct reception of the next frame possible.
Page 551: Operation In Clock Synchronous Mode
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.5 Operation in Clock Synchronous Mode Figure 23.21 shows the data format for clock synchronous serial data communications. In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data.
Page 552: Cts And Rts Functions
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.5.2 CTS and RTS Functions In the CTS function, CTSn# pin input is used to control reception/transmission start when the clock source is the internal clock. Setting the SPMR.CTSE bit to 1 enables the CTS function. When the CTS function is enabled, placing the low level on the CTSn# pin causes reception/transmission to start.
Page 553: Sci Initialization (Clock Synchronous Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.5.3 SCI Initialization (Clock Synchronous Mode) Before transmitting and receiving data, start by writing the initial value 00h to the SCR register and then continue through the procedure for SCI given in Figure 23.22 . Whenever the operating mode or transfer format is changed, the SCR register must be initialized before the change is made.
Page 554: Serial Data Transmission (Clock Synchronous Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.5.4 Serial Data Transmission (Clock Synchronous Mode) Figure 23.22 , Figure 23.23 , and Figure 23.24 show an example of the operation for serial transmission in clock synchronous mode. In serial data transmission, the SCI operates as described below. 1.
Page 555 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Synchronization clock Serial data Bit 0 Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 SCR.TE bit TXI interrupt flag (IRn in ICU SSR.TEND flag TXI interrupt request TXI interrupt TXI interrupt TXI interrupt generated...
Page 556 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Synchronization clock Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 Serial data (TIE = 1) TXI interrupt flag (IRn in ICU* (TIE = 0) SSR.TEND flag TEI interrupt Data written to TDR in...
Page 557 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) [ 1 ] SCI initialization: [ 1 ] Initialization Set data transmission. [ 2 ] Writing transmit data write to TDR by a TXI interrupt Start transmission request: When transmit data is transferred from TDR to TSR, a transmit data empty interrupt (TXI) request is [ 2 ] generated.
Page 558: Serial Data Reception (Clock Synchronous Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.5.5 Serial Data Reception (Clock Synchronous Mode) Figure 23.27 and Figure 23.28 show an example of SCI operation for serial reception in clock synchronous mode. In serial data reception, the SCI operates as described below. 1.
Page 559 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Synchronization clock Serial data Bit 6 Bit 7 Bit 0 Bit 7 Bit 0 RXI interrupt flag (IRn in ICU* SSR.ORER flag RXI interrupt RXI interrupt ERI interrupt request RDR data read in RXI request request generated by overrun error...
Page 560 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Figure 23.29 shows a sample flowchart for serial data reception. [ 1 ] SCI initialization: Initialization Make input port-pin settings for pins to be used [ 1 ] as RXDn pins. Start data reception [ 2 ] [ 3 ] Receive error processing: If a receive error occurs, read the ORER flag in...
Page 561: Simultaneous Serial Data Transmission And Reception (Clock Synchronous Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.5.6 Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode) Figure 23.30 shows a sample flowchart for simultaneous serial transmit and receive operations in clock synchronous mode. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
Page 562: Operation In Smart Card Interface Mode
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.6 Operation in Smart Card Interface Mode The SCI supports smart card (IC card) interfaces conforming to ISO/IEC 7816-3 (standard for Identification Cards), as an extended function of the SCI. Smart card interface mode can be selected using the appropriate register. 23.6.1 Sample Connection Figure 23.31 shows a sample connection between a smart card (IC card) and this MCU.
Page 563: Data Format (Except In Block Transfer Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.6.2 Data Format (Except in Block Transfer Mode) Figure 23.32 shows the data transfer formats in smart card interface mode.  One frame consists of 8-bit data and a parity bit in asynchronous mode. ...
Page 564: Block Transfer Mode
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) For communications with IC cards of the direct convention type and inverse convention type, follow the procedure below. (1) Direct Convention Type For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB first as the start character, as shown in Figure 23.33 .
Page 565: Receive Data Sampling Timing And Reception Margin
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.6.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode. In this mode, the SCI can operate on a base clock with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit rate according to the settings of the BCP2 bit in the SCMR register and the BCP[1:0] bits in the SMR register (the frequency is always 16 times the bit rate in normal asynchronous mode).
Page 566: Sci Initialization (Smart Card Interface Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.6.5 SCI Initialization (Smart Card Interface Mode) Initialize the SCI following the example of flowchart shown in Figure 23.36 . Be sure to initialize the SCI before switching from transmission mode to reception mode and vice versa. Even if the RE bit is set to 0, the RDR register is not initialized.
Page 567: Serial Data Transmission (Except In Block Transfer Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.6.6 Serial Data Transmission (Except in Block Transfer Mode) Serial data transmission in smart card interface mode (except in block transfer mode), in that an error signal is sampled and data can be retransmitted, is different from that in non-smart card interface mode. Figure 23.37 shows the data retransfer operation during transmission.
Page 568 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Note that the SSR.TEND flag is set in different timings depending on the GM bit setting in the SMR register. Figure 23.38 shows the TEND flag generation timing. I/O data SSR.TEND flag Guard (TXI interrupt) time...
Page 569 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Start Initialization Start data transmission SSR.ERS flag = 0? Error processing TXI interrupt Write transmit data to TDR Write all transmit data SSR.ERS flag = 0? Error processing TXI interrupt Set bits TIE, RIE, and TE in SCR to 0 Figure 23.39 Sample Smart Card Interface Transmission Flowchart...
Page 570: Serial Data Reception (Except In Block Transfer Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.6.7 Serial Data Reception (Except in Block Transfer Mode) Serial data reception in smart card interface mode is similar to that in non-smart card interface mode. Figure 23.40 shows the data retransfer operation in reception mode. 1.
Page 571 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Start Initialization Start data reception SSR.ORER = 0 and SSR.PER = 0? Error processing RXI interrupt Read data from RDR All data received? Set bits RIE and RE in SCR to 0 Figure 23.41 Sample Smart Card Interface Reception Flowchart R01UH0421EJ0120 Rev.1.20...
Page 572: Clock Output Control
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.6.8 Clock Output Control Clock output can be fixed using the CKE[1:0] bits in the SCR register when the GM bit in the SMR register is 1. Specifically, the minimum width of a clock pulse can be specified. Figure 23.42 shows an example of clock output fixing timing when the CKE[0] bit is controlled with GM = 1 and CKE[1] = 0.
Page 573: Operation In Simple I C Mode
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.7 Operation in Simple I C Mode Simple I C-bus format is composed of 8 data bits and an acknowledge bit. By continuing into a slave-address frame after a start condition or restart condition, a master device is able to specify a slave device as the partner for communications. The currently specified slave device remains valid until a new slave device is specified or a stop condition is satisfied.
Page 574: Generation Of Start, Restart, And Stop Conditions
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.7.1 Generation of Start, Restart, and Stop Conditions Writing 1 to the IICSTAREQ bit in the SIMR3 register causes the generation of a start condition. The generation of a start condition proceeds through the following operations. ...
Page 575 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Figure 23.45 shows the timing of operations in the generation of start, restart, and stop conditions. SSCLn SSDAn SIMR3.IICSTAREQ SIMR3.IICRSTAREQ SIMR3.IICSTPREQ SIMR3.IICSDAS[1:0] 11b 01b SIMR3.IICSCLS[1:0] Restart-condition generated Stop-condition generated Start-condition generated interrupt request interrupt request interrupt request Figure 23.45...
Page 576: Clock Synchronization
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.7.2 Clock Synchronization The SSCLn line may be placed at the low level in the case of a wait inserted by a slave device as the other side of transfer. Setting the IICCSC bit in the SIMR2 register to 1 applies control to obtain synchronization when the levels of the internal SSCLn clock signal and the level being input on the SSCLn pin differ.
Page 577: Ssda Output Delay
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.7.3 SSDA Output Delay The IICDL[4:0] bits in the SIMR1 register can be used to set a delay for output on the SSDAn pin relative to falling edges of output on the SSCLn pin. Delay-time settings from 0 to 31 are selectable, representing periods of the corresponding numbers of cycles of the clock signal from the on-chip baud rate generator (derived by frequency-dividing the base clock, PCLK, by the divisor selected by the CKS[1:0] bits in the SMR register).
Page 578: Sci Initialization (Simple I 2 C Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.7.4 SCI Initialization (Simple I C Mode) Before transferring data, write the initial value (00h) to SCR and initialize the interface following the example shown in Figure 23.48 . When changing the operating mode, transfer format, and so on, be sure to set SCR to its initial value before proceeding with the changes.
Page 579: Operation In Master Transmission (Simple I 2 C Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.7.5 Operation in Master Transmission (Simple I C Mode) Figure 23.49 and Figure 23.50 show examples of operations in master transmission and Figure 23.51 is a flowchart showing the procedure for data transmission. Refer to Table 23.32 for more information on the STI interrupt. When 10-bit slave addresses are in use, steps [3] and [4] in Figure 23.51 are repeated twice.
Page 580 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) [ 1 ] Initialization for simple I C mode Initialization [ 1 ] For transmission, set the SCR.RIE bit to 0 (RXI and ERI interrupts requests are disabled) Start of transmission [ 2 ] Generate a start condition.
Page 581: Master Reception (Simple I 2 C Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.7.6 Master Reception (Simple I C Mode) Figure 23.52 shows an example of operations in simple I C mode master reception and Figure 23.53 is a flowchart showing the procedure for master reception. The value of the SIMR2.IICINTM bit is assumed to be 1 (use reception and transmission interrupts).
Page 582 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Initialization [ 1 ] [ 1 ] Initialization for simple I C mode: Set the RIE bit in SCR to 0. Start of reception [ 2 ] Generate a start condition. [ 3 ] Writing to TDR: Simultaneously set the SIMR3.IICSTAREQ bit Writing the slave address and value for the R/W bit to...
Page 583: Operation In Simple Spi Mode
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.8 Operation in Simple SPI Mode As an extended function, the SCI supports a simple SPI mode that handles transfer among one or multiple master devices and multiple slave devices. Making the settings for clock synchronous mode (SCMR.SMIF = 0, SIMR1.IICM = 0, SMR.CM = 1) plus setting the SSE bit in the SPMR to 1 places the SCI in simple SPI mode.
Page 584: States Of Pins In Master And Slave Modes
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.8.1 States of Pins in Master and Slave Modes The direction (input or output) of pins for the simple SPI mode interface differs according to whether the device is a master (SCR.CKE[1:0] = 00b or 01b and SPMR.MSS = 0) or slave (SCR.CKE[1:0] = 10b or 11b and SPMR.MSS = 1). Table 23.28 lists the states of pins according to the mode and the level on the SSn# pin.
Page 585: Relationship Between Clock And Transmit/Receive Data
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.8.4 Relationship between Clock and Transmit/Receive Data The CKPOL and CKPH bits in the SPMR can be used to set up the clock for use in transmission and reception in four different ways. The relation between the clock signal and the transmission and reception of data is shown in Figure 23.55 .
Page 586: Sci Initialization (Simple Spi Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.8.5 SCI Initialization (Simple SPI Mode) The procedure is the same as for initialization in clock synchronous mode Figure 23.22 , Sample SCI Initialization Flowchart. The CKPOL and CKPH bits in the SPMR must be set to ensure that the kind of clock signal they select is suitable for both master and slave devices.
Page 587: Extended Serial Mode Control Section: Description Of Operation
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.9 Extended Serial Mode Control Section: Description of Operation 23.9.1 Serial Transfer Protocol In conjunction with the SCIe module, the extended serial mode control section of the SCIf module can realize the serial transfer protocol composed of Start Frames and Information Frames that is shown in Figure 23.56 .
Page 588: Transmitting A Start Frame
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.9.2 Transmitting a Start Frame Figure 23.57 shows an example of operations to transmit a Start Frame, which is composed of the Break Field low width, Control Field 0, and Control Field 1. Figure 23.58 and Figure 23.59 are flowcharts for the transmission of a Start Frame.
Page 589 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Start Set 1 to SCI12.ESMER.ESME Enable the extended serial mode control section. Set SCI12.CR2.RTS[1:0], BCCS[1:0], Set the timing of sampling for RXDX12 reception, clock for bus collision detection, and DFCS[2:0] and sampling clock for the RXDX12 signal’s digital filter. Set SCI12.PCR.SHARPS, RXDXPS, Set the RXDX12 and TXDX12 pins.
Page 590 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Set 1 to SCI12.TCR.TCST Start the timer counter and output of the Break Field low width. The STR.BFDF flag is set to 1 on output of the Break Field low width. At this time, if the ICR.BFDIE bit is 1, an SCIX0 interrupt is generated.
Page 591: Receiving A Start Frame
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.9.3 Receiving a Start Frame The extended serial mode control section is capable of receiving Start Frames with the structures listed in Table 23.29 . Table 23.29 Structures of Start Frames Bit Setting Structures of Start Frames CF0RE Information Frame...
Page 592 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Start Frame Information Frame Break Field low width Control Field 0 Control Field 1 Data Field RXDX12 pin 8 bits 8 bits SCI12 RXD 8 bits 8 bits input Write 1 to CR3.SDST Set to 0 after Break Field low width detection...
Page 593 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Start Set 1 to SCI12.ESMER.ESME Enable the extended serial mode control section. Set whether to include the Break Field and Control Field 0 Set SCI12.CR1.BFE and CF0RE in the Start Frame. Select the data for comparison with Control Field 1 and the Set SCI12.CR1.CF1DS[1:0] and PIBE presence or absence of a priority interrupt bit.
Page 594 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Start the timer counter so that determining the Set 1 to SCI12.TCR.TCST Break Field is possible. Set 1 to SCI12.CR3.SDST Begin detection of the Start Frame. The SCI12.STR.BFDF flag is set to 1 on detection of the Break Field low width.
Page 595 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Initialization CR3.SDST = 1 Break Field [Break Field low width] detected Non-match Control Field 0 CR3.SDST = 1 [CF0RR] matches [CF0DR] Non-match Control Field 1 [CF1RR] matches [PCF1DR, SCF1DR], or both the priority interrupt bit is detected. Information Frame Figure 23.63 State Transitions When Receiving a Start Frame...
Page 596: Priority Interrupt Bit
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.9.3.1 Priority Interrupt Bit Figure 23.64 shows an example of operation in Start Frame reception where a priority interrupt bit is in use. Setting the CR1.PIBE bit to 1 enables the use of a priority interrupt bit. Operations of the extended serial mode control section in start Frame reception where a priority interrupt bit is in use are as described below.
Page 597: Detection Of Bus Collisions
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.9.4 Detection of Bus Collisions Detection of bus collisions operate for cases where output of the Break Field low width and transmission of data by the SCI12 are in progress when the ESMER.ESME bit and the SCI12.SCI.TE bit are set to 1. Figure 23.65 shows an example of operations with bus collision detection.
Page 598: Digital Filter For Input On The Rxdx12 Pin
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.9.5 Digital Filter for Input on the RXDX12 Pin Signals input through the RXDX12 pin can be passed through a digital filter before they are conveyed to the internal circuits. The digital filter consists of three flip-flop circuit stages connected in series and a match-detecting circuit. The CR2.DFCS[2:0] bits select the sampling clock for the RXDX12 pin input signals.
Page 599: Bit Rate Measurement
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.9.6 Bit Rate Measurement The bit rate measurement function measures the intervals between rising and falling edges and between falling and rising edges of the signal input from the RXDX12 pin. Figure 23.67 shows an example of operations for bit rate measurement. (1) Writing 1 to the CR0.BRME bit enables bit rate measurement.
Page 600: Selectable Timing For Sampling Data Received Through Rxdx12
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.9.7 Selectable Timing for Sampling Data Received through RXDX12 The extended serial mode control section provides a way of adjusting the timing for the sampling of data received through the RXDX12 pin of an SCI12 by setting the CR2.RTS[1:0] bits to select the rising edges of 8th, 10th, 12th, or 14th cycle of the SCI base clock.
Page 601: Timer
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.9.8 Timer The timer has the following operating modes. (1) Break Field Low Width Output Mode This mode is for output through the TXDX12 pin of the low level over the Break Field low width at the transmission of a Start Frame.
Page 602 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) (2) Break Field Low Width Determination Mode This mode is for determining the Break Field low width in the input signal on the RXDX12 pin at the reception of a Start Frame. Setting the TMR.TOMS[1:0] bits to 01b switches operation to Break Field low width determination mode. The TMR.TCSS[2:0] bits select the clock source for the counter.
Page 603: 23.10 Noise Cancellation Function
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.10 Noise Cancellation Function Figure 23.71 shows the configuration of the noise filter used for noise cancellation. The noise filter consists of two stages of flip-flop circuits and a match-detection circuit. When the level on the pin matches in three consecutive samples taken at the set sampling interval, the matching level continues to be conveyed internally until the level on the pin again matches in three consecutive samples.
Page 604: 23.11 Interrupt Sources
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.11 Interrupt Sources 23.11.1 Buffer Operations for TXI and RXI Interrupts If the conditions for a TXI and RXI interrupt are satisfied while the interrupt status flag in the interrupt controller is 1, the SCI does not output the interrupt request but retains it internally (with a capacity for retention of one request per source).
Page 605: Interrupts In Smart Card Interface Mode
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.11.3 Interrupts in Smart Card Interface Mode Table 23.31 lists interrupt sources in smart card interface mode. A transmit end interrupt (TEI) request cannot be used in this mode. Table 23.31 SCI Interrupt Sources Name Interrupt Source Interrupt Flag...
Page 606: Interrupts In Simple I C Mode
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.11.4 Interrupts in Simple I C Mode C mode are listed in Table 23.32 . The STI interrupt is allocated to the transmit end The interrupt sources in simple I interrupt (TEI) request. The receive error interrupt (ERI) request cannot be used. The DTC can also be used to handle transfer in simple I C mode.
Page 607: Interrupt Requests From The Extended Serial Mode Control Section
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.11.5 Interrupt Requests from the Extended Serial Mode Control Section The extended serial mode control section has a total of six types of interrupt request for generating the SCIX0 interrupt (Break Field low width detected), SCIX1 interrupt (Control Field 0 match, Control Field 1 match, priority interrupt bit detected), SCIX2 interrupt (bus collision detected), and SCIX3 interrupt (valid edge detected).
Page 608: 23.12 Usage Notes
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.12 Usage Notes 23.12.1 Setting the Module Stop Function Module stop control register B (MSTPCRB) is used to stop and start SCI operations. With the value after a reset, SCI operations are stopped. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 609: Restrictions On Clock Synchronous Transmission (Clock Synchronous Mode And Simple Spi Mode)
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.12.6 Restrictions on Clock Synchronous Transmission (Clock Synchronous Mode and Simple SPI Mode) When the external clock source is used as a synchronization clock, the following restrictions apply. (1) Start of transmission Update TDR by the CPU or DTC and wait for at least five PCLK cycles before allowing the transmit clock to be input (refer to Figure 23.72 ).
Page 610: Restrictions On Using Dtc
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.12.7 Restrictions on Using DTC When using the DTC to read RDR, be sure to set the receive data full interrupt (RXI) as the activation source of the relevant SCI. 23.12.8 Notes on Starting Transfer At the point where transfer starts when the interrupt status flag (IRn.IR bit) in the interrupt controller is 1, follow the procedure below to clear interrupt requests before permitting operations (by setting the SCR.TE or SCR.RE bit to 1).
Page 611 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Data transmission [ 1 ] Data being transmitted is lost halfway. Data can be [ 1 ] All data transmitted? normally transmitted from the CPU by setting the TE bit in SCR to 1, reading SSR, and writing data to TDR after canceling software standby mode.
Page 612 RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Transition to software standby Software standby mode mode canceled Port mode register (PMR) setting SCR.TE The level at transition to software standby mode is retained SCKn output pin TXDn output pin The level before transition to Port input/output High output Stop...
Page 613: External Clock Input In Clock Synchronous Mode And Simple Spi Mode
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) Data reception [ 1 ] Data being received is invalid. [ 1 ] RXI interrupt Read receive data in RDR SCR.RE = 0 Make transition to software standby mode [ 2 ] Setting for the module stop state is included. [ 2 ] Cancel software standby mode Change operating mode?
Page 614: Limitations On Simple Spi Mode
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.12.11 Limitations on Simple SPI Mode (1) Master Mode  Use a resistor to pull up or pull down the clock line matching the initial settings for the transfer clock set by the SPMR.CKPH and CKPOL bits when the SPMR.SSE bit is 1.
Page 615: Limitation 2 On Usage Of The Extended Serial Mode Control Section
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.12.13 Limitation 2 on Usage of the Extended Serial Mode Control Section An SCIe interrupt request is generated even if the extended serial mode is enabled. However, the SCIe interrupt should not be used during reception of a Start Frame because SCIf uses an SCIe interrupt request. The two ways of dealing with this are described below.
Page 616: Note On Stopping Reception When The Rts Function Is In Use
RX110 Group 23. Serial Communications Interface (SCIe, SCIf) 23.12.15 Note on Stopping Reception When the RTS Function is in Use One clock cycle of PCLK is required for the time from setting the SCR.RE bit to 0 to stopping the RTS signal generator. When reading the RDR (or RDRL) register after setting the SCR.RE bit to 0, confirm that the RE bit has been set to 0 before reading the RDR (or RDRL) register to prevent these two processes from being performed consecutively.
Page 617: I C-Bus Interface (Riic)
RX110 Group 24. I C-bus Interface (RIIC) C-bus Interface (RIIC) This MCU has a single-channel I C-bus interface (RIIC). The RIIC module conforms with the NXP I C-bus (Inter-IC bus) interface and provides a subset of its functions. In this section, “PCLK” is used to refer to PCLKB. 24.1 Overview Table 24.1 lists the specifications of the RIIC, Figure 24.1 shows a block diagram of the RIIC, and Figure 24.2 shows...
Page 618 RX110 Group 24. I C-bus Interface (RIIC) Table 24.1 RIIC Specifications (2/2) Item Description Low power consumption Module stop state can be set. function  Four RIIC operating modes Master transmit mode, master receive mode, slave transmit mode, and slave receive mode PCLK CKS[2:0] ICMR1...
Page 619 RX110 Group 24. I C-bus Interface (RIIC) Power supply for pull-up (VCC to 5 V) SCLin SCLout# SDAin SDAout# (Master) SCLin SCLin SCLout# SCLout# SDAin SDAin SDAout# SDAout# (Slave 1) (Slave 2) Figure 24.2 I/O Pin Connection to the External Circuit (I C-bus Configuration Example) The input level of the signals for RIIC is CMOS when I C-bus is selected (ICMR3.SMBS bit is 0), or TTL when SMBus...
Page 620: Register Descriptions
RX110 Group 24. I C-bus Interface (RIIC) 24.2 Register Descriptions 24.2.1 C-bus Control Register 1 (ICCR1) Address(es): RIIC0.ICCR1 0008 8300h IICRST SOWP SCLO SDAO SCLI SDAI Value after reset: Symbol Bit Name Description SDAI SDA Line Monitor 0: SDA0 line is low. 1: SDA0 line is high.
Page 621 RX110 Group 24. I C-bus Interface (RIIC) CLO Bit (Extra SCL Clock Cycle Output) This bit is used to output an extra SCL clock cycle for debugging or error processing. Normally, set the bit to 0. Setting the bit to 1 in a normal communication state causes a communication error. For details on this function, refer to section 24.11.2, Extra SCL Clock Cycle Output Function .
Page 622: I 2 C-Bus Control Register 2 (Iccr2)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.2 C-bus Control Register 2 (ICCR2) Address(es): RIIC0.ICCR2 0008 8301h BBSY — — Value after reset: Symbol Bit Name Description — Reserved This bit is read as 0. The write value should be 0. Start Condition Issuance 0: Does not request to issue a start condition.
Page 623 RX110 Group 24. I C-bus Interface (RIIC) RS Bit (Restart Condition Issuance Request) This bit is used to request that a restart condition be issued in master mode. When this bit is set to 1 to request to issue a restart condition, a restart condition is issued when the BBSY flag is set to 1 (bus busy state) and the MST bit is set to 1 (master mode).
Page 624 RX110 Group 24. I C-bus Interface (RIIC) TRS Bit (Transmit/Receive Mode) This bit indicates transmit or receive mode. The RIIC is in receive mode when the TRS bit is set to 0 and is in transmit mode when the bit is set to 1. Combination of this bit and the MST bit indicates the operating mode of the RIIC.
Page 625 RX110 Group 24. I C-bus Interface (RIIC) BBSY Flag (Bus Busy Detection Flag) The BBSY flag indicates whether the I C-bus is occupied (bus busy state) or released (bus free state). This bit is set to 1 when the SDA0 line changes from high to low under the condition of SCL0 line = high, assuming that a start condition has been issued.
Page 626: I 2 C-Bus Mode Register 1 (Icmr1)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.3 C-bus Mode Register 1 (ICMR1) Address(es): RIIC0.ICMR1 0008 8302h MTWP CKS[2:0] BCWP BC[2:0] Value after reset: Symbol Bit Name Description b2 to b0 BC[2:0] Bit Counter R/W* 0 0 0: 9 bits 0 0 1: 2 bits 0 1 0: 3 bits 0 1 1: 4 bits...
Page 627: I 2 C-Bus Mode Register 2 (Icmr2)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.4 C-bus Mode Register 2 (ICMR2) Address(es): RIIC0.ICMR2 0008 8303h DLCS SDDL[2:0] TMWE TMOH TMOL TMOS Value after reset: Symbol Bit Name Description TMOS Timeout Detection Time Select 0: Long mode is selected. 1: Short mode is selected.
Page 628 RX110 Group 24. I C-bus Interface (RIIC) TMOH Bit (Timeout H Count Control) This bit is used to enable or disable the internal counter of the timeout function to count up while the SCL0 line is held high when the timeout function is enabled (ICFER.TMOE bit is 1). TMWE Bit (Timeout Internal Counter Write Enable) This bit is used to select whether or not to allocate the timeout internal counter (TMOCNTL/TMOCNTU) to the address of the slave address register (SARL0/SARU0).
Page 629: I 2 C-Bus Mode Register 3 (Icmr3)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.5 C-bus Mode Register 3 (ICMR3) Address(es): RIIC0.ICMR3 0008 8304h WAIT RDRFS ACKW SMBS ACKBT ACKBR NF[1:0] Value after reset: Symbol Bit Name Description b1, b0 NF[1:0] Noise Filter Stage Select b1 b0 0 0: Noise of up to one IIC ...
Page 630 RX110 Group 24. I C-bus Interface (RIIC) ACKBR Bit (Receive Acknowledge) This bit is used to store the acknowledge bit information received from the receive device in transmit mode. [Setting condition]  When 1 is received as the acknowledge bit with the ICCR2.TRS bit set to 1 [Clearing conditions] ...
Page 631: I 2 C-Bus Function Enable Register (Icfer)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.6 C-bus Function Enable Register (ICFER) Address(es): RIIC0.ICFER 0008 8305h — SCLE NACKE SALE NALE MALE TMOE Value after reset: Symbol Bit Name Description TMOE Timeout Function Enable 0: The timeout function is disabled. 1: The timeout function is enabled.
Page 632 RX110 Group 24. I C-bus Interface (RIIC) NACKE Bit (NACK Reception Transfer Suspension Enable) This bit is used to specify whether to continue or discontinue the transfer operation when NACK is received from the slave device in transmit mode. Normally, set this bit to 1. When NACK is received with the NACKE bit set to 1, the next transfer operation is suspended.
Page 633: I 2 C-Bus Status Enable Register (Icser)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.7 C-bus Status Enable Register (ICSER) Address(es): RIIC0.ICSER 0008 8306h HOAE — DIDE — GCAE SAR2E SAR1E SAR0E Value after reset: Symbol Bit Name Description SAR0E Slave Address Register 0 Enable 0: Slave address in registers SARL0 and SARU0 is disabled. 1: Slave address in registers SARL0 and SARU0 is enabled.
Page 634 RX110 Group 24. I C-bus Interface (RIIC) HOAE Bit (Host Address Enable) This bit is used to specify whether to ignore received host address (0001 000b) when the ICMR3.SMBS bit is 1. When this bit is set to 1 while the ICMR3.SMBS bit is 1, if the received slave address matches the host address, the RIIC recognizes the received slave address as the host address independently of the slave addresses set in registers SARLy and SARUy (y = 0 to 2) and performs the receive operation.
Page 635: I 2 C-Bus Interrupt Enable Register (Icier)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.8 C-bus Interrupt Enable Register (ICIER) Address(es): RIIC0.ICIER 0008 8307h TEIE NAKIE SPIE STIE ALIE TMOIE Value after reset: Symbol Bit Name Description TMOIE Timeout Interrupt Request Enable 0: Timeout interrupt (TMOI) request is disabled. 1: Timeout interrupt (TMOI) request is enabled.
Page 636 RX110 Group 24. I C-bus Interface (RIIC) TEIE Bit (Transmit End Interrupt Request Enable) This bit is used to enable or disable transmit end interrupt (TEI) requests when the ICSR2.TEND flag is set to 1. An TEI interrupt request is canceled by setting the TEND flag or the TEIE bit to 0. TIE Bit (Transmit Data Empty Interrupt Request Enable) This bit is used to enable or disable transmit data empty interrupt (TXI) requests when the ICSR2.TDRE flag is set to 1.
Page 637: I 2 C-Bus Status Register 1 (Icsr1)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.9 C-bus Status Register 1 (ICSR1) Address(es): RIIC0.ICSR1 0008 8308h — — AAS2 AAS1 AAS0 Value after reset: Symbol Bit Name Description AAS0 Slave Address 0 Detection Flag 0: Slave address 0 is not detected. R/(W) 1: Slave address 0 is detected.
Page 638 RX110 Group 24. I C-bus Interface (RIIC) For 10-bit address format: SARUy.FS bit = 1  When the received slave address does not match a value of (11110b + SARUy.SVA[1:0] bits) with the ICSER.SARyE bit set to 1 (slave address y detection enabled) This flag is set to 0 at the rising edge of the ninth SCL clock cycle in the first byte.
Page 639 RX110 Group 24. I C-bus Interface (RIIC) (host address detection is enabled) This flag is set to 0 at the rising edge of the ninth SCL clock cycle in the first byte.  When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset R01UH0421EJ0120 Rev.1.20 Page 639 of 968 Jul 29, 2016...
Page 640: I 2 C-Bus Status Register 2 (Icsr2)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.10 C-bus Status Register 2 (ICSR2) Address(es): RIIC0.ICSR2 0008 8309h TDRE TEND RDRF NACKF STOP START TMOF Value after reset: Symbol Bit Name Description TMOF Timeout Detection Flag 0: Timeout is not detected. R/(W) 1: Timeout is detected.
Page 641 RX110 Group 24. I C-bus Interface (RIIC) [Setting conditions] When master arbitration-lost detection is enabled: ICFER.MALE = 1  When the internal SDA output state does not match the SDA0 line level at the rising edge of SCL clock except for the ACK period during data (including slave address) transmission in master transmit mode (when the SDA0 line is driven low while the internal SDA output is at a high level (the SDA0 pin is in the high-impedance state)) ...
Page 642 RX110 Group 24. I C-bus Interface (RIIC) NACKF Flag (NACK Detection Flag) [Setting condition]  When acknowledge is not received (NACK is received) from the receive device in transmit mode with the ICFER.NACKE bit set to 1 (transfer suspension enabled) [Clearing conditions] ...
Page 643: Slave Address Register Ly (Sarly) (Y = 0 To 2)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2) Address(es): RIIC0.SARL0 0008 830Ah, RIIC0.SARL1 0008 830Ch, RIIC0.SARL2 0008 830Eh SVA[6:0] SVA0 Value after reset: Symbol Bit Name Description SVA0 10-Bit Address LSB A slave address is set.
Page 644: Slave Address Register Uy (Saruy) (Y = 0 To 2)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2) Address(es): RIIC0.SARU0 0008 830Bh, RIIC0.SARU1 0008 830Dh, RIIC0.SARU2 0008 830Fh — — — — — SVA[1:0] Value after reset: Symbol Bit Name Description 7-Bit/10-Bit Address Format Select 0: The 7-bit address format is selected.
Page 645: I 2 C-Bus Bit Rate Low-Level Register (Icbrl)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.13 C-bus Bit Rate Low-Level Register (ICBRL) Address(es): RIIC0.ICBRL 0008 8310h — — — BRL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 BRL[4:0] Bit Rate Low-Level Period Low-level period of SCL clock b7 to b5 —...
Page 646: I 2 C-Bus Bit Rate High-Level Register (Icbrh)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.14 C-bus Bit Rate High-Level Register (ICBRH) Address(es): RIIC0.ICBRH 0008 8311h — — — BRH[4:0] Value after reset: Symbol Bit Name Description b4 to b0 BRH[4:0] Bit Rate High-Level Period High-level period of SCL clock b7 to b5 —...
Page 647 RX110 Group 24. I C-bus Interface (RIIC) Table 24.5 Examples of ICBRH/ICBRL Settings for Transfer Rate Operating Frequency PCLK (MHz) Transfer 12.5 Rate (kbps) CKS[2:0] ICBRH ICBRL CKS[2:0] ICBRH ICBRL CKS[2:0] ICBRH ICBRL 100b 22 (F6h) 25 (F9h) 101b 13 (EDh) 15 (EFh) 101b 16 (F0h)
Page 648: I 2 C-Bus Transmit Data Register (Icdrt)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.15 C-bus Transmit Data Register (ICDRT) Address(es): RIIC0.ICDRT 0008 8312h Value after reset: When the ICDRT register detects a space in the I C-bus shift register (ICDRS), it transfers the transmit data that has been written to the ICDRT register to the ICDRS register and starts transmitting data in transmit mode.
Page 649: Timeout Internal Counter (Tmocntl/Tmocntu)
RX110 Group 24. I C-bus Interface (RIIC) 24.2.18 Timeout Internal Counter (TMOCNTL/TMOCNTU) Address(es): RIIC0.TMOCNTL 0008 830Ah, RIIC0.TMOCNTU 0008 830Bh  TMOS = 0 (Long mode) TMOCNTU TMOCNTL Value after reset:  TMOS = 1 (Short mode) TMOCNTU TMOCNTL — — Value after reset: Note: These registers are assigned to the same addresses as those of registers SARL0 and SARU0.
Page 650: Operation
RX110 Group 24. I C-bus Interface (RIIC) 24.3 Operation 24.3.1 Communication Data Format The I C-bus format consists of 8-bit data and 1-bit acknowledge. The first byte following a start condition or restart condition is an address byte used to specify a slave device with which the master device communicates. The specified slave is valid until a new slave is specified or a stop condition is issued.
Page 651: Initial Settings
RX110 Group 24. I C-bus Interface (RIIC) 24.3.2 Initial Settings Before starting data transmission and reception, initialize the RIIC according to the procedure in Figure 24.5 . Set the ICCR1.ICE bit to 1 (internal reset) after setting the ICCR1.IICRST bit to 1 (RIIC reset) with the ICCR1.ICE bit set to 0 (SCL0 and SDA0 pins in inactive state).
Page 652: Master Transmit Operation
RX110 Group 24. I C-bus Interface (RIIC) 24.3.3 Master Transmit Operation In master transmit operation, the RIIC outputs the SCL clock and transmitted data signals as the master device, and the slave device returns acknowledgments. Figure 24.6 shows an example of usage of master transmission and Figure 24.7 to Figure 24.9 show the timing of operations in master transmission.
Page 653 RX110 Group 24. I C-bus Interface (RIIC) Master transmission [1] Initial settings Initial settings ICCR2.BBSY = 0? [2] Check I C-bus occupation and issue a start condition. ICCR2.ST = 1 ICSR2.NACKF = 0? ICSR2.TDRE = 1? [3] Transmit slave address and W (first byte). TMOCNTL = 00h [4] Check ACK and set transmit data.
Page 654 RX110 Group 24. I C-bus Interface (RIIC) Automatic low-hold (to prevent wrong transmission) SCL0 SDA0 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + W) Transmit data (DATA 1) Transmit data (DATA 2) TDRE TEND RDRF ICDRT 7-bit address + W DATA 1...
Page 655: Master Receive Operation
RX110 Group 24. I C-bus Interface (RIIC) SCL0 SDA0 A/NA DATA n-2 DATA n-1 DATA n BBSY Transmit data (DATA n) Transmit data (DATA n-1) TDRE TEND RDRF DATA n-1 ICDRT DATA n ICDRS DATA n-2 DATA n-1 DATA n XXXX (Initial value/final receive data) ICDRR 0 (ACK)
Page 656 RX110 Group 24. I C-bus Interface (RIIC) Because the ICSR2.NACKF flag being 1 at this time indicates that no slave device recognized the address or there was an error in communications, write 1 to the ICCR2.SP bit to issue a stop condition. For master reception from a device with a 10-bit address, start by using master transmission to issue the 10-bit address, and then issue a restart condition.
Page 657 RX110 Group 24. I C-bus Interface (RIIC) Master reception starts Initial settings (1) Initial settings ICCR2.BBSY = 0? (2) Check I C-bus occupation and issue a start condition. ICCR2.ST = 1 ICSR2.TDRE = 1? TMOCNTL = 00h *1, *2 TMOCNTU = 00h Write the ICDRT register (3) Transmit the slave address followed by R and check ACK.
Page 658 RX110 Group 24. I C-bus Interface (RIIC) Master reception starts Initial settings (1) Initial settings ICCR2.BBSY = 0? (2) Check that the bus is free and issue a start condition. ICCR2.ST = 1 ICSR2.TDRE = 1? TMOCNTL = 00h TMOCNTU = 00h Write data to ICDRT register (3) Transmit the slave address followed by R and check ACK.
Page 659 RX110 Group 24. I C-bus Interface (RIIC) Automatic low hold Master transmit mode Master receive mode (to prevent wrong transmission) SCL0 SDA0 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + R) TDRE Receive data (7-bit address + R) Receive data (DATA 1) TEND RDRF...
Page 660 RX110 Group 24. I C-bus Interface (RIIC) Automatic low hold (WAIT) Automatic low hold (WAIT) SCL0 NACK SDA0 DATA n-2 DATA n-1 DATA n BBSY TDRE Receive data (DATA n-2) Receive data (DATA n-1) Receive data (DATA n) TEND RDRF XXXX (last data for transmission ICDRT [7-bit addresses + R/Upper 10 bits + R])
Page 661: Slave Transmit Operation
RX110 Group 24. I C-bus Interface (RIIC) 24.3.5 Slave Transmit Operation In slave transmit operation, the master device outputs the SCL clock, the RIIC transmits data as a slave device, and the master device returns acknowledgments. Figure 24.15 shows an example of usage of slave transmission and Figure 24.16 and Figure 24.17 show the timing of operations in slave transmission.
Page 662 RX110 Group 24. I C-bus Interface (RIIC) Slave transmission [1] Initial settings Initial settings ICSR2.NACKF=0? ICSR2.TDRE=1? TMOCNTL = 00h [2], [3] Check ACK bit and set transmit data TMOCNTU = 00h (Checking of ACK not necessary immediately after address is received) Write data to ICDRT register All data transmitted? ICSR2.TEND=1?
Page 663 RX110 Group 24. I C-bus Interface (RIIC) Slave receive mode Slave transmit mode Automatic low hold (to prevent wrong transmission) SCL0 SDA0 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (DATA 1) Transmit data (DATA 2) TDRE TEND RDRF AASy XXXX (Initial value/last data for transmission)
Page 664: Slave Receive Operation
RX110 Group 24. I C-bus Interface (RIIC) 24.3.6 Slave Receive Operation In slave receive operation, the master device outputs the SCL clock and transmit data, and the RIIC returns acknowledgments as a slave device. Figure 24.18 shows an example of usage of slave reception and Figure 24.19 and Figure 24.20 show the timing of operations in slave reception.
Page 665 RX110 Group 24. I C-bus Interface (RIIC) Slave reception [1] Initial settings Initial settings ICSR2.STOP = 0? ICSR2.RDRF = 1? ICSR2.RDRF = 1? [2], [3], [4] Read receive data (Dummy read first) TMOCNTL = 00h TMOCNTL = 00h TMOCNTU = 00h TMOCNTU = 00h Read ICDRR register Read ICDRR register (last data)
Page 666 RX110 Group 24. I C-bus Interface (RIIC) Automatic low hold (to prevent failure to receive data) SCL0 SDA0 7-bit slave address DATA 1 DATA 2 BBSY TDRE Receive data (7-bit address + W) Receive data (DATA 1) TEND RDRF AASy ICDRT XXXX (Initial value/last data for transmission) 7-bit address + W...
Page 667: Scl Synchronization Circuit
RX110 Group 24. I C-bus Interface (RIIC) 24.4 SCL Synchronization Circuit In generation of the SCL clock, the RIIC starts counting out the value for width at high level specified in the ICBRH register when it detects a rising edge on the SCL0 line and drives the SCL0 line low once counting of the width at high level is complete.
Page 668: Sda Output Delay Function
RX110 Group 24. I C-bus Interface (RIIC) 24.5 SDA Output Delay Function The RIIC module incorporates a function for delaying output on the SDA line. The delay can be applied to all output (issuing of the start, restart, and stop conditions, data, and the ACK and NACK signals) on the SDA line. With the SDA output delay function, SDA output is delayed from detection of a falling edge of the SCL signal to ensure that the SDA signal is output within the interval over which the SCL clock is at the low level.
Page 669: Digital Noise Filter Circuit
RX110 Group 24. I C-bus Interface (RIIC) 24.6 Digital Noise Filter Circuit The states of the SCL0 and SDA0 pins are conveyed to the internal circuitry through analog noise-filter and digital noise- filter circuits. Figure 24.23 is a block diagram of the digital noise-filter circuit. The on-chip digital noise-filter circuit of the RIIC consists of four flip-flop circuit stages connected in series and a match- detection circuit.
Page 670: Address Match Detection
RX110 Group 24. I C-bus Interface (RIIC) 24.7 Address Match Detection The RIIC can set three unique slave addresses in addition to the general call address and host address, and also can set 7- bit or 10-bit slave addresses. 24.7.1 Slave-Address Match Detection The RIIC can set three unique slave addresses, and has a slave address detection function for each unique slave address.
Page 671 RX110 Group 24. I C-bus Interface (RIIC) [10-bit address format: Slave reception] SCL0 Upper 2 bits 10-bit slave address (lower 8 bits) Data SDA0 BBSY Address match AASy Receive data (lower addresses) TDRE RDRF Read ICDRR register (Dummy read [lower addresses]) [10-bit address format: Slave transmission] 1 to 8 SCL0...
Page 672: Detection Of The General Call Address
RX110 Group 24. I C-bus Interface (RIIC) 24.7.2 Detection of the General Call Address The RIIC has a facility for detecting the general call address (0000 000b + 0 (write)). This is enabled by setting the ICSER.GCAE bit to 1. If the address received after a start or restart condition is issued is 0000 000b + 1 (read) (start byte), the RIIC recognizes this as the address of a slave device with an “all-zero”...
Page 673: Device-Id Address Detection
RX110 Group 24. I C-bus Interface (RIIC) 24.7.3 Device-ID Address Detection The RIIC module has a facility for detecting device-ID addresses conformant with the I C-bus specification (Rev. 03). When the RIIC receives 1111 100b as the first byte after a start condition or restart condition was issued with the ICSER.DIDE bit set to 1, the RIIC recognizes the address as a device ID, sets the ICSR1.DID flag to 1 on the rising edge of the eighth SCL clock cycle when the following R/W# bit is 0, and then compares the second and subsequent bytes with its own slave address.
Page 674 RX110 Group 24. I C-bus Interface (RIIC) [Device-ID reception] SCL0 SDA0 Address BBSY Slave address match AASy Device-ID match (1111 100b + R) Device-ID match (1111 100b + W) Receive data (7-bit address/lower 10 bits) TDRE RDRF Read ICDRR register (Dummy read [7-bit address/lower 10 bits]) [When address received after a restart condition is detected does not match the device-ID ] SCL0...
Page 675: Host Address Detection
RX110 Group 24. I C-bus Interface (RIIC) 24.7.4 Host Address Detection The RIIC has a function to detect the host address while the SMBus is operating. When the ICSER.HOAE bit is set to 1 while the ICMR3.SMBS bit is 1, the RIIC can detect the host address (0001 000b) in slave receive mode (bits MST and TRS in the ICCR2 register are 00b).
Page 676: Automatic Low-Hold Function For Scl
RX110 Group 24. I C-bus Interface (RIIC) 24.8 Automatic Low-Hold Function for SCL 24.8.1 Function to Prevent Wrong Transmission of Transmit Data If the shift register (ICDRS) is empty when data have not been written to the I C-bus transmit data register (ICDRT) with the RIIC in transmission mode (ICCR2.TRS bit is 1), the SCL0 line is automatically held at the low level over the intervals shown below.
Page 677: Nack Reception Transfer Suspension Function
RX110 Group 24. I C-bus Interface (RIIC) 24.8.2 NACK Reception Transfer Suspension Function The RIIC has a function to suspend transfer operation when NACK is received in transmit mode (ICCR2.TRS bit is 1). This function is enabled when the ICFER.NACKE bit is set to 1 (transfer suspension enabled). If the next transmit data has already been written (ICSR2.TDRE flag is 0) when NACK is received, next data transmission at the falling edge of the ninth SCL clock cycle is automatically suspended.
Page 678 RX110 Group 24. I C-bus Interface (RIIC) (1) 1-Byte Receive Operation and Automatic Low-Hold Function Using the WAIT Bit When the ICMR3.WAIT bit is set to 1, the RIIC performs 1-byte receive operation using the WAIT bit function. Furthermore, when the ICMR3.RDRFS bit is 0, the RIIC automatically sends the ICMR3.ACKBT bit value for the acknowledge bit in the period from the falling edge of the eighth SCL clock cycle to the falling edge of the ninth SCL clock cycle, and automatically holds the SCL0 line low at the falling edge of the ninth SCL clock cycle using the WAIT bit function.
Page 679: Arbitration-Lost Detection Functions
RX110 Group 24. I C-bus Interface (RIIC) 24.9 Arbitration-Lost Detection Functions In addition to the normal arbitration-lost detection function defined by the I C-bus specification, the RIIC has functions to prevent double-issue of a start condition, to detect arbitration-lost during transmission of NACK, and to detect arbitration-lost in slave transmit mode.
Page 680 RX110 Group 24. I C-bus Interface (RIIC) [When slave addresses conflict] Transmit data mismatch Release SCL/SDA (Arbitration lost) SCL0 SDA0 SCL0 SDA0 Data Data BBSY Address match Address mismatch AASy TDRE Clear AL flag to 0 [When data transmission conflicts after general call address is sent] Transmit data mismatch Release SCL/SDA (Arbitration lost)
Page 681: Function To Detect Loss Of Arbitration During Nack Transmission (Nale Bit)
RX110 Group 24. I C-bus Interface (RIIC) 24.9.2 Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit) The RIIC has a function to cause arbitration to be lost if the internal SDA output level does not match the level on the SDA0 line (the high output as the internal SDA output;...
Page 682: Slave Arbitration-Lost Detection (Sale Bit)
RX110 Group 24. I C-bus Interface (RIIC) [Condition for arbitration-lost during NACK transmission]  When the internal SDA output level does not match the SDA0 line (ACK is received) during transmission of NACK (ICMR3.ACKBT bit = 1) 24.9.3 Slave Arbitration-Lost Detection (SALE Bit) The RIIC has a function to cause arbitration to be lost if the data for transmission (i.e.
Page 683: 24.10 Start Condition/Restart Condition/Stop Condition Issuing Function
RX110 Group 24. I C-bus Interface (RIIC) 24.10 Start Condition/Restart Condition/Stop Condition Issuing Function 24.10.1 Issuing a Start Condition The RIIC issues a start condition when the ICCR2.ST bit is set to 1. When the ST bit is set to 1, a start condition issuance request is made and the RIIC issues a start condition when the ICCR2.BBSY flag is 0 (bus free state).
Page 684: Issuing A Stop Condition
RX110 Group 24. I C-bus Interface (RIIC) 24.10.3 Issuing a Stop Condition The RIIC issues a stop condition when the ICCR2.SP bit is set to 1. When the SP bit is set to 1, a stop condition issuance request is made and the RIIC issues a stop condition when the ICCR2.BBSY flag is 1 (bus busy state) and the ICCR2.MST bit is 1 (master mode).
Page 685: 24.11 Bus Hanging
RX110 Group 24. I C-bus Interface (RIIC) 24.11 Bus Hanging If the clock signals from the master and slave devices go out of synchronization due to noise or other factors, the I C-bus might hang with a fixed level on the SCL0 line and/or SDA0 line. As measures against the bus hanging, the RIIC has a timeout function to detect hanging by monitoring the SCL0 line, a function for the output of an extra SCL clock cycle to release the bus from a hung state due to clock signals being out of synchronization, the RIIC reset function, and internal reset function.
Page 686 RX110 Group 24. I C-bus Interface (RIIC) [Timeout function] Start internal Start internal Start internal Start internal Start internal Start internal counter counter counter counter counter counter Clear internal Clear internal Clear internal Clear internal Clear internal Clear internal Clear internal counter counter counter...
Page 687: Extra Scl Clock Cycle Output Function
RX110 Group 24. I C-bus Interface (RIIC) 24.11.2 Extra SCL Clock Cycle Output Function In master mode, the RIIC module has a facility for the output of extra SCL clock cycles to release the SDA0 line of the slave device from being held at the low level due to the master being out of synchronization with the slave device. This function is mainly used in master mode to release the SDA0 line of the slave device from the state of being fixed to the low level by including extra cycles of SCL output from the RIIC with single cycles of the SCL clock as the unit if the RIIC cannot issue a stop condition because the slave device is holding the SDA0 line at the low level.
Page 688: Riic Reset And Internal Reset
RX110 Group 24. I C-bus Interface (RIIC) 24.11.3 RIIC Reset and Internal Reset The RIIC module incorporates a function for resetting itself. There are two types of reset. One is referred to as an RIIC reset; this initializes all registers including the ICCR2.BBSY flag. The other is referred to as an internal reset; this releases the RIIC from the slave-address matched state and initializes the internal counter while retaining other settings.
Page 689: 24.12 Smbus Operation
RX110 Group 24. I C-bus Interface (RIIC) 24.12 SMBus Operation The RIIC is available for data communication conforming to the SMBus (Version 2.0). To perform SMBus communication, set the ICMR3.SMBS bit to 1. To use the transfer rate within a range of 10 kbps to 100 kbps of the SMBus specification, set the ICMR1.CKS[2:0] bits, the ICBRH register, and the ICBRL register.
Page 690: Packet Error Code (Pec)
RX110 Group 24. I C-bus Interface (RIIC) SMBus specification : Total clock low-level extended period (slave device) LOW:SEXT : Total clock low-level extended period (master device) LOW:MEXT Start Stop LOW:SEXT LOW:MEXT LOW:MEXT LOW:MEXT LOW:MEXT SCL0 Data A/NA 7-bit slave address Data SDA0 BBSY...
Page 691: 24.13 Interrupt Sources
RX110 Group 24. I C-bus Interface (RIIC) 24.13 Interrupt Sources The RIIC issues four types of interrupt request: transfer error or event generation (arbitration-lost, NACK detection, timeout detection, start condition detection, and stop condition detection), receive data full, transmit data empty, and transmit end.
Page 692: 24.14 Resets And Register And Function States When Issuing Each Condition
RX110 Group 24. I C-bus Interface (RIIC) 24.14 Resets and Register and Function States When Issuing Each Condition The RIIC can be reset by MCU reset, RIIC reset, and internal reset functions. Table 24.8 lists the register and function states when issuing each reset or condition. Table 24.8 Register and Function States When Issuing Each Reset or Condition Start Condition/...
Page 693: 24.15 Usage Notes
RX110 Group 24. I C-bus Interface (RIIC) 24.15 Usage Notes 24.15.1 Setting Module Stop Function Module stop state can be entered or released using module stop control register B (MSTPCRB). The initial setting is for operation of the RIIC to be stopped. RIIC register access is enabled by releasing the module stop state. For details on module stop control register B, refer to section 11, Low Power Consumption .
Page 694: Serial Peripheral Interface (Rspi)
RX110 Group 25. Serial Peripheral Interface (RSPI) Serial Peripheral Interface (RSPI) In this section, “PCLK” is used to refer to PCLKB. 25.1 Overview This MCU includes one channel of Serial Peripheral Interface (RSPI). The RSPI channels are capable of high-speed, full-duplex synchronous serial communications with multiple processors and peripheral devices.
Page 695 RX110 Group 25. Serial Peripheral Interface (RSPI) Table 25.1 RSPI Specifications (2/2) Item Description  Interrupt sources Interrupt sources Receive buffer full interrupt Transmit buffer empty interrupt RSPI error interrupt (mode fault, overrun, or parity error) RSPI idle interrupt (RSPI idle) ...
Page 696 RX110 Group 25. Serial Peripheral Interface (RSPI) Internal Module data bus peripheral bus SPBR SPRX SPTX SPCR SSLP SPPCR Baud rate PCLK generator SPSR SPDR SPSCR Parity circuit SPSSR SPDCR SPCKD SSLND Shift register SPND SPCR2 SPCMD Selector Transmission/ reception controller Normal Clock Loopback...
Page 697 RX110 Group 25. Serial Peripheral Interface (RSPI) Table 25.2 lists the I/O pins used in the RSPI. The RSPI automatically switches the I/O direction of the SSLA0 pin. SSLA0 is set as an output when the RSPI is a single master and as an input when the RSPI is a multi-master or a slave.
Page 698: Register Descriptions
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.2 Register Descriptions 25.2.1 RSPI Control Register (SPCR) Address(es): RSPI0.SPCR 0008 8380h SPTIE SPEIE MSTR MODF SPRIE TXMD SPMS Value after reset: Symbol Bit Name Description SPMS RSPI Mode Select 0: SPI operation (4-wire method) 1: Clock synchronous operation (3-wire method) TXMD Communications Operating Mode...
Page 699 RX110 Group 25. Serial Peripheral Interface (RSPI) MODFEN Bit (Mode Fault Error Detection Enable) The MODFEN bit enables or disables the detection of mode fault error (refer to section 25.3.8, Error Detection ). In addition, the RSPI determines the I/O direction of the SSLA0 to SSLA3 pins based on combinations of the MODFEN and MSTR bits (refer to section 25.3.2, Controlling RSPI Pins ).
Page 700: Rspi Slave Select Polarity Register (Sslp)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.2.2 RSPI Slave Select Polarity Register (SSLP) Address(es): RSPI0.SSLP 0008 8381h — — — — SSL3P SSL2P SSL1P SSL0P Value after reset: Symbol Bit Name Description SSL0P SSL0 Signal Polarity Setting 0: SSL0 signal is active low 1: SSL0 signal is active high SSL1P SSL1 Signal Polarity Setting...
Page 701: Rspi Pin Control Register (Sppcr)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.2.3 RSPI Pin Control Register (SPPCR) Address(es): RSPI0.SPPCR 0008 8382h — — MOIFE MOIFV — — SPLP2 SPLP Value after reset: Symbol Bit Name Description SPLP RSPI Loopback 0: Normal mode 1: Loopback mode (data is inverted for transmission) SPLP2 RSPI Loopback 2 0: Normal mode...
Page 702: Rspi Status Register (Spsr)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.2.4 RSPI Status Register (SPSR) Address(es): RSPI0.SPSR 0008 8383h SPRF — SPTEF — PERF MODF IDLNF OVRF Value after reset: Symbol Bit Name Description OVRF Overrun Error Flag 0: No overrun error occurs R/(W) 1: An overrun error occurs IDLNF...
Page 703 RX110 Group 25. Serial Peripheral Interface (RSPI) Slave mode  The SPCR.SPE bit is 0 (disables the RSPI function) MODF Flag (Mode Fault Error Flag) Indicates the occurrence of a mode fault error. [Setting condition] Multi-master mode  When the input level of the SSLAi pin changes to the active level while the SPCR.MSTR bit is 1 (master mode) and the SPCR.MODFEN bit is 1 (mode fault error detection is enabled), the RSPI detects a mode fault error Slave mode ...
Page 704: Rspi Data Register (Spdr)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.2.5 RSPI Data Register (SPDR) Address(es): RSPI0.SPDR 0008 8384h Value after reset: Value after reset: Address(es): RSPI0.SPDR.H 0008 8384h Value after reset: SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI. When accessing in longwords (the SPLW bit is 1), access SPDR.
Page 705 RX110 Group 25. Serial Peripheral Interface (RSPI) Furthermore, if the data length is other than 32 bits, bits not referred to in SPTXn (n = 0 to 3) are stored in the corresponding bits in SPRXn. For example, if the data length is 9 bits, received data are stored in the SPRXn[8:0] bits and the SPTXn[31:9] bits are stored in the SPRXn[31:9] bits.
Page 706 RX110 Group 25. Serial Peripheral Interface (RSPI) (b) Reading SPDR can be read to read the value of a receive buffer (SPRXn) or a transmit buffer (SPTXn). The setting of the RSPI receive/transmit data select bit in the RSPI data control register (SPDCR.SPRDTD) selects whether reading is of the receive or transmit buffer.
Page 707: Rspi Sequence Control Register (Spscr)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.2.6 RSPI Sequence Control Register (SPSCR) Address(es): RSPI0.SPSCR 0008 8388h — — — — — SPSLN[2:0] Value after reset: Symbol Bit Name Description b2 to b0 SPSLN[2:0] RSPI Sequence Length b0 Sequence Length Referenced SPCMD0 to SPCMD7 (No.) 0 0 0: 1 0→0→…...
Page 708: Rspi Sequence Status Register (Spssr)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.2.7 RSPI Sequence Status Register (SPSSR) Address(es): RSPI0.SPSSR 0008 8389h — SPECM[2:0] — SPCP[2:0] Value after reset: Symbol Bit Name Description b2 to b0 SPCP[2:0] RSPI Command Pointer 0 0 0: SPCMD0 0 0 1: SPCMD1 0 1 0: SPCMD2 0 1 1: SPCMD3 1 0 0: SPCMD4...
Page 709: Rspi Bit Rate Register (Spbr)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.2.8 RSPI Bit Rate Register (SPBR) Address(es): RSPI0.SPBR 0008 838Ah Value after reset: SPBR sets the bit rate in master mode. If the contents of SPBR are changed while both the SPCR.MSTR and SPCR.SPE bits are 1, subsequent operations should not be performed.
Page 710: Rspi Data Control Register (Spdcr)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.2.9 RSPI Data Control Register (SPDCR) Address(es): RSPI0.SPDCR 0008 838Bh SPLW SPRDT — — — — SPFC[1:0] Value after reset: Symbol Bit Name Description b1, b0 SPFC[1:0] Number of Frames b1 b0 0 0: 1 frame Specification 0 1: 2 frames 1 0: 3 frames...
Page 711 RX110 Group 25. Serial Peripheral Interface (RSPI) Table 25.4 Settable Combinations of SPSLN[2:0] Bits and SPFC[1:0] Bits Number of Frames in Number of Frames at which Transmit Buffer or Receive Setting SPSLN[2:0] SPFC[1:0] a Single Sequence Buffer Status Becomes “Has Valid Data” 000b 000b 000b...
Page 712: Rspi Clock Delay Register (Spckd)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.2.10 RSPI Clock Delay Register (SPCKD) Address(es): RSPI0.SPCKD 0008 838Ch — — — — — SCKDL[2:0] Value after reset: Symbol Bit Name Description b2 to b0 SCKDL[2:0] RSPCK Delay Setting 0 0 0: 1 RSPCK 0 0 1: 2 RSPCK 0 1 0: 3 RSPCK 0 1 1: 4 RSPCK...
Page 713: Rspi Slave Select Negation Delay Register (Sslnd)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.2.11 RSPI Slave Select Negation Delay Register (SSLND) Address(es): RSPI0.SSLND 0008 838Dh — — — — — SLNDL[2:0] Value after reset: Symbol Bit Name Description b2 to b0 SLNDL[2:0] SSL Negation Delay Setting 0 0 0: 1 RSPCK 0 0 1: 2 RSPCK 0 1 0: 3 RSPCK...
Page 714: Rspi Next-Access Delay Register (Spnd)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.2.12 RSPI Next-Access Delay Register (SPND) Address(es): RSPI0.SPND 0008 838Eh — — — — — SPNDL[2:0] Value after reset: Symbol Bit Name Description b2 to b0 SPNDL[2:0] RSPI Next-Access Delay Setting 0 0 0: 1 RSPCK + 2 PCLK 0 0 1: 2 RSPCK + 2 PCLK 0 1 0: 3 RSPCK + 2 PCLK 0 1 1: 4 RSPCK + 2 PCLK...
Page 715: Rspi Control Register 2 (Spcr2)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.2.13 RSPI Control Register 2 (SPCR2) Address(es): RSPI0.SPCR2 0008 838Fh — — — — SPIIE SPOE SPPE Value after reset: Symbol Bit Name Description SPPE Parity Enable 0: Does not add the parity bit to transmit data and does not check the parity bit of receive data 1: Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0)
Page 716: Rspi Command Registers 0 To 7 (Spcmd0 To Spcmd7)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.2.14 RSPI Command Registers 0 to 7 (SPCMD0 to SPCMD7) Address(es): RSPI0.SPCMD0 0008 8390h, RSPI0.SPCMD1 0008 8392h, RSPI0.SPCMD2 0008 8394h, RSPI0.SPCMD3 0008 8396h, RSPI0.SPCMD4 0008 8398h, RSPI0.SPCMD5 0008 839Ah, RSPI0.SPCMD6 0008 839Ch, RSPI0.SPCMD7 0008 839Eh SCKDE SLNDE SPNDE...
Page 717 RX110 Group 25. Serial Peripheral Interface (RSPI) SPCMDm register is used to set a transfer format for the RSPI in master mode. Each channel has eight RSPI command registers (SPCMD0 to SPCMD7). Some of the bits in SPCMD0 register is used to set a transfer mode for the RSPI in slave mode.
Page 718 RX110 Group 25. Serial Peripheral Interface (RSPI) SPNDEN Bit (RSPI Next-Access Delay Enable) The SPNDEN bit sets the period from the time the RSPI in master mode terminates a serial transfer and sets the SSLAi signal inactive until the RSPI enables the SSLAi signal assertion for the next access (next-access delay). If the SPNDEN bit is 0, the RSPI sets the next-access delay to 1 RSPCK + 2 PCLK.
Page 719: Operation
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3 Operation In this section, the serial transfer period means a period from the beginning of driving valid data to the fetching of the final valid data. 25.3.1 Overview of RSPI Operations The RSPI is capable of synchronous serial transfers in slave mode (SPI operation), single-master mode (SPI operation), multi-master mode (SPI operation), slave mode (clock synchronous operation), and master mode (clock synchronous operation).
Page 720: Controlling Rspi Pins
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.2 Controlling RSPI Pins According to the MSTR, MODFEN, and SPMS bits in SPCR and the ODRn.Bi bit for I/O ports, the RSPI can switch pin states. Table 25.6 lists the relationship between pin states and bit settings. Setting the ODRn.Bi bit for an I/O port to 0 selects CMOS output;...
Page 721: Rspi System Configuration Examples
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.3 RSPI System Configuration Examples 25.3.3.1 Single Master/Single Slave (with This MCU Acting as Master) Figure 25.5 shows a single-master/single-slave RSPI system configuration example when this MCU is used as a master. In the single-master/single-slave configuration, the SSLA0 to SSLA3 output of this MCU (master) are not used. The SSL input of the SPI slave is fixed to the low level, and the SPI slave is maintained in a select state.
Page 722: Single Master/Single Slave (With This Mcu Acting As Slave)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.3.2 Single Master/Single Slave (with This MCU Acting as Slave) Figure 25.6 shows a single-master/single-slave RSPI system configuration example when this MCU is used as a slave. When this MCU is to operate as a slave, the SSLA0 pin is used as SSL input. The SPI master drives the RSPCK and MOSI.
Page 723: Single Master/Multi-Slave (With This Mcu Acting As Master)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.3.3 Single Master/Multi-Slave (with This MCU Acting as Master) Figure 25.8 shows a single-master/multi-slave RSPI system configuration example when this MCU is used as a master. In the example of Figure 25.8 , the RSPI system is comprised of this MCU (master) and four slaves (SPI slave 0 to SPI slave 3).
Page 724: Single Master/Multi-Slave (With This Mcu Acting As Slave)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.3.4 Single Master/Multi-Slave (with This MCU Acting as Slave) Figure 25.9 shows a single-master/multi-slave RSPI system configuration example when this MCU is used as a slave. In the example of Figure 25.9 , the RSPI system is comprised of an SPI master and two MCUs (slave X and slave Y). The SPCK and MOSI outputs of the SPI master are connected to the RSPCKA and MOSIA inputs of the MCUs (slave X and slave Y).
Page 725: Multi-Master/Multi-Slave (With This Mcu Acting As Master)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.3.5 Multi-Master/Multi-Slave (with This MCU Acting as Master) Figure 25.10 shows a multi-master/multi-slave RSPI system configuration example when this MCU is used as a master. In the example of Figure 25.10 , the RSPI system is comprised of two MCUs (master X and master Y) and two SPI slaves (SPI slave 1 and SPI slave 2).
Page 726: Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation) (With This Mcu Acting As Master)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.3.6 Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation) (with This MCU Acting as Master) Figure 25.11 shows a master (clock synchronous operation)/slave (clock synchronous operation) RSPI system configuration example when this MCU is used as a master. In the master (clock synchronous operation)/slave (clock synchronous operation) configuration, SSLA0 to SSLA3 of this MCU (master) are not used.
Page 727: Data Format
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.4 Data Format The RSPI’s data format depends on the settings in RSPI command register m (SPCMDm) (m = 0 to 7) and the parity enable bit in RSPI control register 2 (SPCR2.SPPE). Regardless of whether the MSB or LSB is first, the RSPI treats the range from the LSB bit in the RSPI data register (SPDR) to the selected data length as transfer data.
Page 728: When Parity Is Disabled (Spcr2.Sppe = 0)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.4.1 When Parity is Disabled (SPCR2.SPPE = 0) When parity is disabled, data for transmission are copied to the shift register with no prior processing. A description of the connection between the RSPI data register (SPDR) and the shift register in terms of the combination of MSB or LSB first and data length is given below.
Page 729 RX110 Group 25. Serial Peripheral Interface (RSPI) (2) MSB First Transfer (24-Bit Data) Figure 25.15 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity disabled, 24 bits as the RSPI data length for an example that is not 32 bits, and MSB first selected. In transmission, the lower-order 24 bits (T23 to T00) from the current stage of the transmit buffer are copied to the shift register.
Page 730 RX110 Group 25. Serial Peripheral Interface (RSPI) (3) LSB First Transfer (32-Bit Data) Figure 25.16 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity disabled, an RSPI data length of 32 bits, and LSB first selected. In transmission, bits T31 to T00 from the current stage of the transmit buffer are reordered bit by bit to obtain the order T00 to T31 for copying to the shift register.
Page 731 RX110 Group 25. Serial Peripheral Interface (RSPI) (4) LSB First Transfer (24-Bit Data) Figure 25.17 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity disabled, 24 bits as the RSPI data length for an example that is not 32 bits, and LSB first selected. In transmission, the lower-order 24 bits (T23 to T00) from the current stage of the transmit buffer are reordered bit by bit to obtain the order T00 to T23 for copying to the shift register.
Page 732: When Parity Is Enabled (Spcr2.Sppe = 1)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.4.2 When Parity is Enabled (SPCR2.SPPE = 1) When parity is enabled, the lowest-order bit of the data for transmission becomes a parity bit. Hardware calculates the value of the parity bit. (1) MSB First Transfer (32-Bit Data) Figure 25.18 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity enabled, an RSPI data length of 32 bits, and MSB first selected.
Page 733 RX110 Group 25. Serial Peripheral Interface (RSPI) (2) MSB First Transfer (24-Bit Data) Figure 25.19 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity enabled, 24 bits as the RSPI data length for an example that is not 32 bits, and MSB first selected. In transmission, the value of the parity bit (P) is calculated from bits T23 to T01.
Page 734 RX110 Group 25. Serial Peripheral Interface (RSPI) (3) LSB First Transfer (32-Bit Data) Figure 25.20 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity enabled, an RSPI data length of 32 bits, and LSB first selected. In transmission, the value of the parity bit (P) is calculated from bits T30 to T00.
Page 735 RX110 Group 25. Serial Peripheral Interface (RSPI) (4) LSB First Transfer (24-Bit Data) Figure 25.21 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity enabled, 24 bits as the RSPI data length for an example that is not 32 bits, and LSB first selected. In transmission, the value of the parity bit (P) is calculated from bits T22 to T00.
Page 736: Transfer Format
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.5 Transfer Format 25.3.5.1 CPHA = 0 Figure 25.22 shows a sample transfer format for the serial transfer of 8-bit data when the SPCMDm.CPHA bit is 0. Note that clock synchronous operation (the SPCR.SPMS bit is 1) should not performed when the RSPI operates in slave mode (SPCR.MSTR = 0) and the CPHA bit is 0.
Page 737: Cpha = 1
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.5.2 CPHA = 1 Figure 25.23 shows a sample transfer format for the serial transfer of 8-bit data when the SPCMDm.CPHA bit is 1. However, when the SPCR.SPMS bit is 1, the SSLAi signals are not used, and only the three signals RSPCKA, MOSIA, and MISOA handle communications.
Page 738: Communications Operating Mode
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.6 Communications Operating Mode Full-duplex synchronous serial communications or transmit operations only can be selected by the communications operating mode select bit (SPCR.TXMD). The SPDR access shown in Figure 25.24 and Figure 25.25 indicate the condition of access to the SPDR register, where W denotes a write cycle.
Page 739: Transmit Operations Only (Spcr.txmd = 1)
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.6.2 Transmit Operations Only (SPCR.TXMD = 1) Figure 25.25 shows an example of operation when the communications operating mode select bit (SPCR.TXMD) is set to 1. In the example in Figure 25.25 , the RSPI performs an 8-bit serial transfer in which the SPDCR.SPFC[1:0] bits are 00b, the SPCMDm.CPHA bit is 1, and the SPCMDm.CPOL bit is 0.
Page 740: Transmit Buffer Empty/Receive Buffer Full Interrupts
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.7 Transmit Buffer Empty/Receive Buffer Full Interrupts Figure 25.26 shows an example of operation of the transmit buffer empty interrupt (SPTI) and the receive buffer full interrupt (SPRI). The SPDR register access shown in Figure 25.26 indicates the condition of access to the SPDR register, where W denotes a write cycle, and R a read cycle.
Page 741 RX110 Group 25. Serial Peripheral Interface (RSPI) (5) When SPDR is read in the receive buffer full interrupt routine or in the receive buffer full detecting process by polling the SPRF flag, the receive data can be read. When the receive data is read, the SPRF flag becomes 0. If transmit data is written to SPDR while the transmit buffer holds data that has not yet been transmitted (the SPTEF flag is 0), the RSPI does not update the data in the transmit buffer.
Page 742: Error Detection
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.8 Error Detection In the normal RSPI serial transfer, the data written to the transmit buffer of SPDR is transmitted, and the received data can be read from the receive buffer of SPDR. If access is made to SPDR, depending on the status of the transmit/receive buffer or the status of the RSPI at the beginning or end of serial transfer, in some cases non-normal transfers can be executed.
Page 743: Overrun Error
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.8.1 Overrun Error If a serial transfer ends when the receive buffer of SPDR is full, the RSPI detects an overrun error, and sets the SPSR.OVRF flag to 1. When the OVRF flag is 1, the RSPI does not copy data from the shift register to the receive buffer so that the data prior to the occurrence of the error is retained in the receive buffer.
Page 744: Parity Error
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.8.2 Parity Error If full-duplex synchronous serial communications is performed with the SPCR.TXMD bit set to 0 and the SPCR2.SPPE bit set to 1, when serial transfer ends, the RSPI checks whether there are parity errors. Upon detecting a parity error in the received data, the RSPI sets the SPSR.PERF flag to 1.
Page 745: Mode Fault Error
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.8.3 Mode Fault Error The RSPI operates in multi-master mode when the SPCR.MSTR bit is 1, the SPCR.SPMS bit is 0, and the SPCR.MODFEN bit is 1. If the active level is input with respect to the SSLA0 input signal of the RSPI in multi-master mode, the RSPI detects a mode fault error irrespective of the status of the serial transfer, and sets the SPSR.MODF flag to 1.
Page 746: Initializing Rspi
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.9 Initializing RSPI If 0 is written to the SPCR.SPE bit or the RSPI sets the SPE bit to 0 because of the detection of a mode fault error, the RSPI disables the RSPI function, and initializes some of the module functions. When a system reset is generated, the RSPI initializes all of the module functions.
Page 747: Spi Operation
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.10 SPI Operation 25.3.10.1 Master Mode Operation The only difference between single-master mode operation and multi-master mode operation lies in mode fault error detection (refer to section 25.3.8, Error Detection ). When operating in single-master mode, the RSPI does not detect mode fault errors whereas the RSPI running in multi-master mode does detect mode fault errors.
Page 748 RX110 Group 25. Serial Peripheral Interface (RSPI) (3) Sequence Control The transfer format that is employed in master mode is determined by SPSCR, SPCMDm, SPBR, SPCKD, SSLND, and SPND registers. SPSCR is a register used to determine the sequence configuration for serial transfers that are executed by the RSPI in master mode.
Page 749 RX110 Group 25. Serial Peripheral Interface (RSPI) Figure 25.31 shows the relationship between the command and the transmit and receive buffers in the sequence of operations specified by the settings in Table 25.4 . SPTX0/SPRX0 Setting 1-1 SPCMD0 Only 1 frame SPTX0/SPRX0 SPTX1/SPRX1 Setting 1-2...
Page 750 RX110 Group 25. Serial Peripheral Interface (RSPI) (4) Burst Transfer If the SPCMDm.SSLKP bit that the RSPI references during the current serial transfer is 1, the RSPI keeps the SSLAi signal level during the serial transfer until the beginning of the SSLAi signal assertion for the next serial transfer. If the SSLAi signal level for the next serial transfer is the same as the SSLAi signal level for the current serial transfer, the RSPI can execute continuous serial transfers while keeping the SSLAi signal assertion status (burst transfer).
Page 751 RX110 Group 25. Serial Peripheral Interface (RSPI) (5) RSPCK Delay (t1) The RSPCK delay value of the RSPI in master mode depends on the SPCMDm.SCKDEN bit setting and the SPCKD register setting. The RSPI determines the SPCMDm register to be referenced during serial transfer by pointer control, and determines an RSPCK delay value during serial transfer by using the SPCMDm.SCKDEN bit and SPCKD, as listed in Table 25.9 .
Page 752 RX110 Group 25. Serial Peripheral Interface (RSPI) (7) Next-Access Delay (t3) The next-access delay value of the RSPI in master mode depends on the SPCMDm.SPNDEN bit setting and the SPND setting. The RSPI determines the SPCMDm register to be referenced during serial transfer by pointer control, and determines a next-access delay value during serial transfer by using the SPCMDm.SPNDEN bit and SPND, as listed in Table 25.11 .
Page 753 RX110 Group 25. Serial Peripheral Interface (RSPI) (8) Initialization Flowchart Figure 25.33 is a flowchart illustrating an example of initialization in SPI operation when the RSPI is used in master mode. For a description of how to set up the interrupt controller and I/O ports, refer to the descriptions given in the individual blocks.
Page 754 RX110 Group 25. Serial Peripheral Interface (RSPI) (9) Software Processing Flow Figure 25.34 to Figure 25.36 show examples of the flow of software processing. (a) Transmit Processing Flow When transmitting data, the CPU will be notified of the completion of data transmission by enabling the SPI interrupt after the last writing of data for transmission.
Page 755 RX110 Group 25. Serial Peripheral Interface (RSPI) (b) Receive Processing Flow The RSPI does not handle receive-only operation, so processing for transmission is required. Pre-transfer processing Processing for reception Start processing End of initial settings for reception SPRI interrupt generated Clear the SPSR.MODF, OVRF, [1] Clear error sources.
Page 756 RX110 Group 25. Serial Peripheral Interface (RSPI) Flow of Error Processing The RSPI has three types of error. When a mode fault error is generated, the SPCR.SPE bit is automatically cleared, stopping operations for transmission and reception. For errors from other sources, however, the SPCR.SPE bit is not cleared and operations for transmission and reception continue;...
Page 757: Slave Mode Operation
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.10.2 Slave Mode Operation (1) Starting a Serial Transfer If the SPCMD0.CPHA bit is 0, when detecting an SSLA0 input signal assertion, the RSPI needs to start driving valid data to the MISOA output signal. For this reason, when the CPHA bit is 0, the assertion of the SSLA0 input signal triggers the start of a serial transfer.
Page 758 RX110 Group 25. Serial Peripheral Interface (RSPI) (4) Burst Transfer If the SPCMD0.CPHA bit is 1, continuous serial transfer (burst transfer) can be executed while retaining the assertion state for the SSLA0 input signal. If the CPHA bit is 1, the period from the first RSPCKA edge to the sampling timing for the reception of the final bit in an SSLA0 signal active state corresponds to a serial transfer period.
Page 759 RX110 Group 25. Serial Peripheral Interface (RSPI) (6) Software Processing Flow Figure 25.38 to Figure 25.40 show examples of the flow of software processing. (a) Transmit Processing Flow Pre-transfer processing Processing for transmission Start processing End of initial settings for transmission SPTI interrupt generated Clear the SPSR.MODF, OVRF, [1] Clear error sources.
Page 760 RX110 Group 25. Serial Peripheral Interface (RSPI) Flow of Error Processing In slave operation, even when a mode fault error is generated, the SPSR.MODF flag can be cleared regardless of the status of the SSLA0 pin. When interrupts are used and an error occurs, if the ICU.IRn.IR flag for the SPTI or SPRI interrupt request is set to 1, clear the ICU.IRn.IR flag in the error processing routine.
Page 761: Clock Synchronous Operation
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.11 Clock Synchronous Operation Setting the SPCR.SPMS bit to 1 selects clock synchronous operation of the RSPI. In clock synchronous operation, the SSLAi pin is not used, and the three pins of RSPCKA, MOSIA, and MISOA handle communications. The SSLAi pin is available as I/O port pins.
Page 762 RX110 Group 25. Serial Peripheral Interface (RSPI) Sequence length Determining Loading transfer format settings setting reference command SPSCR Command pointer control SPCMD0 SPCMD1 SPCMD2 SPCMD3 SPCMD4 CPHA SLNDEN SPNDEN SCKDEN CPOL SPCMD5 SSLND SPND SPCKD BRDV[1:0] SPCMD6 SSLA[2:0] SPCMD7 SSLKP SPB[3:0] LSBF Transfer format determiner...
Page 763 RX110 Group 25. Serial Peripheral Interface (RSPI) Figure 25.43 shows the relationship between the command and the transmit and receive buffers in the sequence of operations specified by the settings in Table 25.4 . SPTX0/SPRX0 Setting 1-1 SPCMD0 Only 1 frame SPTX0/SPRX0 SPTX1/SPRX1 Setting 1-2...
Page 764 RX110 Group 25. Serial Peripheral Interface (RSPI) (4) Initialization Flowchart Figure 25.44 is a flowchart illustrating an example of initialization in clock synchronous operation when the RSPI is used in master mode. For a description of how to set up the interrupt controller and I/O ports, refer to the descriptions given in the individual blocks.
Page 765: Slave Mode Operation
RX110 Group 25. Serial Peripheral Interface (RSPI) (5) Flow of Software Processing Software processing during clock-synchronous master operation is the same as that for SPI master operation. For details, refer to section 25.3.10.1 , (9) Software Processing Flow . Note that mode fault errors will not occur. 25.3.11.2 Slave Mode Operation (1) Starting a Serial Transfer...
Page 766 RX110 Group 25. Serial Peripheral Interface (RSPI) (3) Initialization Flowchart Figure 25.45 is a flowchart illustrating an example of initialization in clock synchronous operation when the RSPI is used in slave mode. For a description of how to set up the interrupt controller and I/O ports, refer to the descriptions given in the individual blocks.
Page 767: Loopback Mode
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.12 Loopback Mode When 1 is written to the SPPCR.SPLP2 bit or SPPCR.SPLP bit, the RSPI shuts off the path between the MISOA pin and the shift register if the SPCR.MSTR bit is 1, and between the MOSIA pin and the shift register if the SPCR.MSTR bit is 0, and connects the input path and output path of the shift register.
Page 768: Self-Diagnosis Of Parity Bit Function
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.13 Self-Diagnosis of Parity Bit Function The parity circuit consists of a parity bit adding unit used for transmit data and an error detecting unit used for received data. In order to detect defects in the parity bit adding unit and error detecting unit of the parity circuit, self-diagnosis is executed for the parity circuit following the flowchart shown in Figure 25.47 .
Page 769: Interrupt Sources
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.3.14 Interrupt Sources The RSPI has interrupt sources of receive buffer full, transmit buffer empty, mode fault, overrun, parity error, and RSPI idle. In addition, the DTC can be activated by the receive buffer full or transmit buffer empty interrupt to perform data transfer.
Page 770: Usage Notes
RX110 Group 25. Serial Peripheral Interface (RSPI) 25.4 Usage Notes 25.4.1 Setting Module Stop Function Module stop control register B (MSTPCRB) can be used to enable or disable the RSPI. Immediately after a reset, operation of the RSPI is disabled. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 771: Crc Calculator (Crc)
RX110 Group 26. CRC Calculator (CRC) CRC Calculator (CRC) The CRC (Cyclic Redundancy Check) calculator generates CRC codes. 26.1 Overview Table 26.1 lists the specifications of the CRC calculator, and Figure 26.1 shows a block diagram of the CRC calculator. Table 26.1 CRC Specifications Item...
Page 772: Register Descriptions
RX110 Group 26. CRC Calculator (CRC) 26.2 Register Descriptions 26.2.1 CRC Control Register (CRCCR) Address(es): 0008 8280h DORCL — — — — GPS[1:0] Value after reset: Symbol Bit Name Description b1, b0 GPS[1:0] CRC Generating Polynomial b1 b0 0 0: No calculation is executed. Switching 0 1: 8-bit CRC (X + X + 1)
Page 773: Crc Data Output Register (Crcdor)
RX110 Group 26. CRC Calculator (CRC) 26.2.3 CRC Data Output Register (CRCDOR) Address(es): 0008 8282h Value after reset: CRCDOR is a readable and writable register. Since its initial value is 0000h, rewrite the CRCDOR register to perform calculation using a value other than the initial value.
Page 774: Operation
RX110 Group 26. CRC Calculator (CRC) 26.3 Operation The CRC calculator generates CRC codes for use in LSB first or MSB first transfer. The following shows examples of generating the CRC code for input data (F0h) using the 16-bit CRC generating polynomial (X + 1).
Page 775 RX110 Group 26. CRC Calculator (CRC) 1. 8-bit serial reception (LSB first) CRC code Data Input 2. Write 83h to the CRC control register (CRCCR) CRCCR CRCDOR Clear CRCDOR 3. Write F0h to the CRC data input register (CRCDIR) CRCDIR CRCDOR CRC code generation 4.
Page 776 RX110 Group 26. CRC Calculator (CRC) 1. 8-bit serial reception (MSB first) Data CRC code Input 2. Write 87h to the CRC control register (CRCCR) CRCCR CRCDOR Clear CRCDOR 3. Write F0h to the CRC data input register (CRCDIR) CRCDIR CRCDOR CRC code generation 4.
Page 777: Usage Notes
RX110 Group 26. CRC Calculator (CRC) 26.4 Usage Notes 26.4.1 Module Stop Function Setting Operation of the CRC calculator can be disabled or enabled using the module stop control register B (MSTPCRB). After a reset, the CRC is in the module stop state. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 778: Overview
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 12-Bit A/D Converter (S12ADb) In this section, “PCLK” is used to refer to PCLKB. 27.1 Overview This MCU includes a 12-bit successive approximation A/D converter. Up to 14 channel analog inputs, temperature sensor outputs, or internal reference voltages can be selected. The 12-bit A/D converter converts a maximum of 14 selected channels of analog inputs, temperature sensor outputs, or internal reference voltages into a 12-bit digital value through successive approximation.
Page 779 RX110 Group 27. 12-Bit A/D Converter (S12ADb) Table 27.1 Specifications of 12-Bit A/D Converter (2/2) Item Specifications  Single scan mode: Operating modes A/D conversion is performed for only once on the analog inputs of up to 14 arbitrarily selected channels. A/D conversion is performed only once on the temperature sensor output.
Page 780 RX110 Group 27. 12-Bit A/D Converter (S12ADb) Table 27.2 Functions of 12-Bit A/D Converter Item Function Analog input channels AN000 to AN004, AN006, AN008 to AN015, temperature sensor output, internal reference voltage A/D conversion Software Software trigger Enabled start conditions Asynchronous trigger ADTRG0# Enabled...
Page 781 RX110 Group 27. 12-Bit A/D Converter (S12ADb) Table 27.3 Input Pins of 12-Bit A/D Converter Pin Name Input Function AVCC0 Input Analog block power supply pin AVSS0 Input Analog block ground pin VREFH0 Input Reference power supply pin VREFL0 Input Reference ground pin AN000 to AN004, AN006, AN008 to AN015 Input...
Page 782: Register Descriptions
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.2 Register Descriptions 27.2.1 A/D Data Registers y (ADDRy) (y = 0 to 4, 6, 8 to 15) ADDRy are 16-bit read-only registers which store the A/D conversion results of channels AN000 to AN004, AN006, AN008 to AN015.
Page 783 RX110 Group 27. 12-Bit A/D Converter (S12ADb) When A/D-converted value addition mode is selected, the AD[13:0] bits in ADDRy show the value added by the A/D- converted value of the respective channels. In A/D-converted value addition mode, the setting of the ADRFMT bit in ADCER becomes invalid and the format of the register becomes left-aligned.
Page 784: A/D Data Duplication Register (Addbldr)
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.2.2 A/D Data Duplication Register (ADDBLDR) ADDBLDR is a 16-bit read-only register used in double trigger mode. ADDBLDR holds the results of A/D conversion of the analog input of the channel selected for data duplication when the conversion is started by the second trigger. ADDBLDR uses the following different formats depending on the setting of the A/D data register format select bit (ADRFMT) in ADCER or A/D-converted value addition mode.
Page 785: A/D Temperature Sensor Data Register (Adtsdr)
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.2.3 A/D Temperature Sensor Data Register (ADTSDR) ADTSDR is a 16-bit read-only register that holds the A/D conversion results of the temperature sensor output. The following different formats are used depending on the settings of the A/D data register format select bit (ADCER.ADRFMT) and A/D-converted value addition mode.
Page 786: A/D Internal Reference Voltage Data Register (Adocdr)
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.2.4 A/D Internal Reference Voltage Data Register (ADOCDR) ADOCDR is a 16-bit read-only register that holds the A/D conversion results of the internal reference voltage. The following different formats are used depending on the setting of the A/D data register format select bit (ADRFMT) in ADCER or A/D-converted value addition mode.
Page 787: A/D Control Register (Adcsr)
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.2.5 A/D Control Register (ADCSR) Address(es): 0008 9000h ADHSC TRGE EXTRG DBLE GBADI ADST ADCS[1:0] ADIE — — DBLANS[4:0] Value after reset: Symbol Bit Name Description b4 to b0 DBLANS[4:0] A/D Conversion Data Select one of 14 analog input channels for A/D conversion data Duplication Channel duplication.
Page 788 RX110 Group 27. 12-Bit A/D Converter (S12ADb) Table 27.4 Relationship between DBLANS[4:0] Bit Settings and Double Trigger Enabled Channels DBLANS[4:0] Duplication Channel DBLANS[4:0] Duplication Channel 00000 AN000 01001 AN009 00001 AN001 01010 AN010 00010 AN002 01011 AN011 00011 AN003 01100 AN012 00100 AN004...
Page 789 RX110 Group 27. 12-Bit A/D Converter (S12ADb) ADCS[1:0] Bits (Scan Mode Select) The ADCS[1:0] bits select the scan mode. In single scan mode, A/D conversion is performed for the analog inputs of a maximum of 14 channels selected with the ADANSA register in the ascending order of the channel number, and when one cycle of A/D conversion is completed for all the selected channels, scan conversion is stopped.
Page 790: A/D Channel Select Register A (Adansa)
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.2.6 A/D Channel Select Register A (ADANSA) Address(es): 0008 9004h ANSA[15:8] — ANSA[6] — ANSA[4:0] Value after reset: Symbol Bit Name Description b4 to b0 ANSA[4:0] A/D Conversion Channel 0 to 4 Select 0: AN000 to AN004 are not subjected to conversion.
Page 791: A/D Channel Select Register B (Adansb)
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.2.7 A/D Channel Select Register B (ADANSB) Address(es): 0008 9014h ANSB[15:8] — ANSB[6] — ANSB[4:0] Value after reset: Symbol Bit Name Description b4 to b0 ANSB[4:0] A/D Conversion Channels 0 to 4 Select 0: AN000 to AN004 are not subjected to conversion.
Page 792: A/D-Converted Value Addition Mode Select Register (Adads)
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.2.8 A/D-Converted Value Addition Mode Select Register (ADADS) Address(es): 0008 9008h ADS[15:8] — ADS[6] — ADS[4:0] Value after reset: Symbol Bit Name Description b4 to b0 ADS[4:0] A/D-Converted Value 0: A/D-converted value addition function for AN000 to AN004 are Addition Channels 0 to 4 not selected.
Page 793: A/D-Converted Value Addition Count Select Register (Adadc)
RX110 Group 27. 12-Bit A/D Converter (S12ADb) Figure 27.2 shows a scanning operation sequence in which both the ADS[2] and ADS[4] bits are set to 1. In continuous scan mode (ADCSR.ADCS[1:0] = 10b), it is assumed that the addition count is set to 3 (ADADC.ADC[1:0] = 11b) and the channels AN000 to AN004, AN006 are selected (ADANSA.ANSA[15:0] = 005Fh).
Page 794: A/D Control Extended Register (Adcer)
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.2.10 A/D Control Extended Register (ADCER) Address(es): 0008 900Eh ADRFM — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description b4 to b0 —...
Page 795: A/D Start Trigger Select Register (Adstrgr)
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.2.11 A/D Start Trigger Select Register (ADSTRGR) Address(es): 0008 9010h — — — — TRSA[3:0] — — — — TRSB[3:0] Value after reset: Symbol Bit Name Description b3 to b0 TRSB[3:0] A/D Conversion Start Trigger Select Select the A/D conversion start trigger for group B in for Group B group scan mode.
Page 796 RX110 Group 27. 12-Bit A/D Converter (S12ADb) Table 27.5 List of A/D Conversion Startup Sources Selected by TRSB[3:0] Bits Module Source Remarks TRSB[3] TRSB[2] TRSB[1] TRSB[0] TRG0AN TGRA input capture/compare match from MTU0 TRG0BN TGRB input capture/compare match B from MTU0 TRGAN TGRA input capture/compare match from MTU0 to MTU2 TRG0EN...
Page 797: A/D Converted Extended Input Control Register (Adexicr)
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.2.12 A/D Converted Extended Input Control Register (ADEXICR) Address(es): 0008 9012h — — — — — — — — — — — — OCSAD TSSAD Value after reset: Symbol Bit Name Description TSSAD Temperature Sensor Output 0: Temperature sensor output A/D-converted value addition A/D-Converted Value Addition...
Page 798: A/D Sampling State Register N (Adsstrn) (N = 0 To 4, 6, L, T, O)
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.2.13 A/D Sampling State Register n (ADSSTRn) (n = 0 to 4, 6, L, T, O) Address(es): ADSSTR0: 0008 9060h, ADSSTR1: 0008 9073h, ADSSTR2: 0008 9074h, ADSSTR3: 0008 9075h, ADSSTR4: 0008 9076h, ADSSTR6: 0008 9078h, ADSSTRL: 0008 9061h, ADSSTRT: 0008 9070h, ADSSTRO: 0008 9071h SST[7:0] Value after reset:...
Page 799: Operation
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.3 Operation 27.3.1 Scanning Operation In scanning, A/D conversion is performed sequentially on the analog inputs of the specified channels. A scan conversion is performed in three operating modes: single scan mode, continuous scan mode, and group scan mode.
Page 800: Single Scan Mode
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.3.2 Single Scan Mode 27.3.2.1 Basic Operation In basic operation of single scan mode, A/D conversion is performed once on the analog input of the specified channels as below. In selected channel scanning, the temperature sensor output A/D conversion select bit (ADEXICR.TSS) and the internal reference voltage A/D conversion select bit (ADEXICR.OCS) should be set to 0 (not selected).
Page 801: A/D Conversion When Temperature Sensor Output Is Selected
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.3.2.2 A/D Conversion When Temperature Sensor Output is Selected To perform A/D conversion of the temperature sensor output, make the following settings before starting conversion operation.  Set the ADCSR.ADST bit to 0 (stops A/D conversion). ...
Page 802: A/D Conversion When Internal Reference Voltage Is Selected
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.3.2.3 A/D Conversion When Internal Reference Voltage is Selected To perform A/D conversion of the internal reference voltage, make the following settings before starting conversion operation.  Set the ADCSR.ADST bit to 0 (stops A/D conversion). ...
Page 803: A/D Conversion In Double Trigger Mode
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.3.2.4 A/D Conversion in Double Trigger Mode In single scan mode with double trigger mode, single scan operation started by synchronous trigger is performed twice as below. The temperature sensor output A/D conversion select bit (ADEXICR.TSS) and the internal reference voltage A/D conversion select bit (ADEXICR.OCS) should be set to 0 (not selected).
Page 804: Continuous Scan Mode
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.3.3 Continuous Scan Mode 27.3.3.1 Basic Operation In basic operation of continuous scan mode, A/D conversion is performed repeatedly on the analog input of the specified channels as below. In continuous scan mode, the temperature sensor output A/D conversion select bit (ADEXICR.TSS) and the internal reference voltage A/D conversion select bit (ADEXICR.OCS) should both be set to 0 (not selected).
Page 805: Group Scan Mode
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.3.4 Group Scan Mode 27.3.4.1 Basic Operation In basic operation of group scan mode, A/D conversion is performed once on the analog inputs of all the specified channels in group A and group B after scanning is started by synchronous trigger as below. Scan operation of each group is similar to the scan operation in single scan mode.
Page 806: A/D Conversion In Double Trigger Mode
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.3.4.2 A/D Conversion in Double Trigger Mode In group scan mode with double trigger mode, single scan operation started by synchronous trigger is performed twice for group A. For group B, single scan operation started by synchronous trigger is performed once. In group scan mode, the group A trigger and group B trigger can be selected using the TRSA[3:0] and TRSB[3:0] bits in ADSTRGR, respectively.
Page 807: Notes On Using Software Trigger
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.3.4.3 Notes on Using Software Trigger When a software trigger is input with double trigger mode selected, scanning of the selected channels is performed, and the S12ADI0 interrupt is output if the ADCSR.ADIE bit is 1 (enables S12ADI0 interrupt), regardless of scanning even or odd number of times.
Page 808: Analog Input Sampling And Scan Conversion Time
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.3.5 Analog Input Sampling and Scan Conversion Time Scan conversion can be activated either by software trigger; the triggers from the MTU, or ADTRG0# (external trigger). After start-of-scanning-delay time (t ) has passed, then starts the A/D conversion process. Figure 27.11 shows the scan conversion timing in single scan mode, in which scan conversion is activated by software trigger or triggers from the MTU.
Page 809: Usage Example Of Automatic Register Clearing Function
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.3.6 Usage Example of Automatic Register Clearing Function Setting the ADCER.ACE bit to 1 automatically clears the A/D data registers (ADDRy, ADOCDR, ADTSDR, and ADDBLDR) to 0000h when the A/D data registers are read by the CPU or DTC. This function enables detection of update failures of the A/D data registers.
Page 810: Starting A/D Conversion With An Asynchronous Trigger
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.3.8 Starting A/D Conversion with an Asynchronous Trigger The A/D conversion can be started by the input of an asynchronous trigger. To start up the A/D converter by an asynchronous trigger, the A/D conversion start trigger select bits (ADSTRGR.TRSA[3:0]) should be set to 0000b and a high-level signal should be input to the asynchronous trigger (ADTRG0# pin), and both the ADCSR.TRGE and ADCSR.EXTRG bits should be set to 1.
Page 811: A/D Conversion Accuracy Definitions
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.5 A/D Conversion Accuracy Definitions The A/D conversion accuracy is defined as below:  Resolution The number of 12-bit A/D converter digital output codes  Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 000000000000 to 000000000001, excluding quantization error.
Page 812: Usage Notes
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.6 Usage Notes 27.6.1 Notes on Reading Data Registers The A/D data registers, A/D data duplication register, A/D temperature sensor data register, and A/D internal reference voltage data register should be read in word units. If a register is read twice in byte units, that is, the higher-order byte and lower-order byte are separately read, the A/D converted value having been read first may disagree with the A/D converted value having been read for the second time.
Page 813: Allowable Impedance Of Signal Source
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.6.8 Allowable Impedance of Signal Source To achieve high-speed conversion of 1.0 μs, the analog input pins of this MCU are designed so that the conversion accuracy is guaranteed if the impedance of the input signal source is 0.3 kΩ or less. If an external capacitor of large capacitance is attached in the application in which only a single pin input is converted in single scan mode, the only load on input is virtually 2.6 kΩ...
Page 814 RX110 Group 27. 12-Bit A/D Converter (S12ADb) Figure 27.15 shows an equivalent circuit of an analog input pin and an external sensor. To perform A/D conversion accurately, charging of the internal capacitor C shown in Figure 27.15 must be completed within the specified period of time.
Page 815: Influence On Absolute Accuracy
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.6.9 Influence on Absolute Accuracy Attaching a capacitor creates coupling with GND and may affect the absolute accuracy when noisy GND is used; therefore, a capacitor should be connected to electrically stable GND such as AVSS0. The filter circuit should be designed so that it does not interfere digital signals or it does not serve as an antenna on the circuit board.
Page 816: Notes On Noise Prevention
RX110 Group 27. 12-Bit A/D Converter (S12ADb) 27.6.12 Notes on Noise Prevention To prevent the analog input pins (AN000 to AN004, AN006, AN008 to AN015) from being destroyed by abnormal voltage such as excessive surge, a capacitor should be inserted between AVCC0 and AVSS0 and between VREFH0 and VREFL0, and a protection circuit should be connected to protect the analog input pins (AN000 to AN004, AN006, AN008 to AN015) as shown Figure 27.17 .
Page 817: Temperature Sensor (Tempsa)
RX110 Group 28. Temperature Sensor (TEMPSA) Temperature Sensor (TEMPSA) 28.1 Overview This MCU includes a temperature sensor. The temperature sensor outputs a voltage which varies with the temperature. The user can obtain the temperature surrounding the MCU using the 12-bit A/D converter to convert the voltage output from the temperature sensor into a digital value.
Page 818: Register Descriptions
RX110 Group 28. Temperature Sensor (TEMPSA) 28.2 Register Descriptions 28.2.1 Temperature Sensor Calibration Data Register (TSCDRH, TSCDRL) Address(es): TSCDRL 007F C0ACh Unique value for each chip Value after reset: Address(es): TSCDRH 007F C0ADh Unique value for each chip Value after reset: The TSCDRH and TSCDRL registers store temperature sensor calibration data measured for each chip at factory shipment.
Page 819: Using The Temperature Sensor
RX110 Group 28. Temperature Sensor (TEMPSA) 28.3 Using the Temperature Sensor The temperature sensor outputs a voltage which varies with the temperature. The user can obtain the temperature surrounding the MCU using the 12-bit A/D converter to convert this voltage into a digital value. 28.3.1 Before Using the Temperature Sensor The temperature characteristics of the temperature sensor are shown below.
Page 820 RX110 Group 28. Temperature Sensor (TEMPSA) T: Measured temperature (°C) Vs: Voltage output by the temperature sensor when the temperature is measured (V) V1: Voltage output by the temperature sensor when Ta = Tj = 88°C and AVCC0 = VREFH0 = 3.3 V (V) Slope: Temperature gradient listed in Table 5.46 ÷...
Page 821: Setting The 12-Bit A/D Converter
RX110 Group 28. Temperature Sensor (TEMPSA) 28.3.2 Setting the 12-Bit A/D Converter The temperature sensor can provide temperature data through the A/D conversion of the temperature sensor output. In order to A/D convert output from the temperature sensor, 12-bit A/D converter registers must be set as follows. ...
Page 822: Data Operation Circuit (Doc)
RX110 Group 29. Data Operation Circuit (DOC) Data Operation Circuit (DOC) 29.1 Overview The data operation circuit (DOC) is used to compare, add, and subtract 16-bit data. Table 29.1 lists the data operation circuit specifications and Figure 29.1 shows a block diagram of the data operation circuit.
Page 823: Register Descriptions
RX110 Group 29. Data Operation Circuit (DOC) 29.2 Register Descriptions 29.2.1 DOC Control Register (DOCR) Address(es): 0008 B080h DOPCF DOPCF DOPCI — — DCSEL OMS[1:0] Value after reset: Symbol Bit Name Description b1, b0 OMS[1:0] Operating Mode Select b1 b0 0: Data comparison mode 1: Data addition mode 0: Data subtraction mode...
Page 824: Doc Data Input Register (Dodir)
RX110 Group 29. Data Operation Circuit (DOC) 29.2.2 DOC Data Input Register (DODIR) Address(es): 0008 B082h Value after reset: DODIR is a 16-bit readable/writable register in which 16-bit data for use in the operations are stored. 29.2.3 DOC Data Setting Register (DODSR) Address(es): 0008 B084h Value after reset: DODSR is a 16-bit readable/writable register.
Page 825: Operation
RX110 Group 29. Data Operation Circuit (DOC) 29.3 Operation 29.3.1 Data Comparison Mode Figure 29.2 shows an example of the steps involved in data comparison mode operation by the data operation circuit. The following is an example of operation when DCSEL is set to 0 (data mismatch is detected as a result of data comparison).
Page 826: Data Addition Mode
RX110 Group 29. Data Operation Circuit (DOC) 29.3.2 Data Addition Mode Figure 29.3 shows an example of the steps involved in data addition mode operation by the data operation circuit. (1) Writing 01b to the DOCR.OMS[1:0] bits selects data addition mode. (2) 16-bit data is set in the DODSR register as the initial value.
Page 827: Data Subtraction Mode
RX110 Group 29. Data Operation Circuit (DOC) 29.3.3 Data Subtraction Mode Figure 29.4 shows an example of the steps involved in data subtraction mode operation by the data operation circuit. (1) Writing 10b to the DOCR.OMS[1:0] bits selects data subtraction mode. (2) 16-bit data is set in the DODSR register as the initial value.
Page 828: Ram
RX110 Group 30. RAM This MCU has an on-chip high-speed static RAM. 30.1 Overview Table 30.1 lists the specifications of the RAM. Table 30.1 RAM Specifications Item Description RAM capacity Max. 16 Kbytes*  Single-cycle access is possible for both reading and writing. Access ...
Page 829: Flash Memory
This function enables rewriting only the selected blocks in the user area and disables the other blocks during self-programming. Note 1. Refer to “PG-FP5 Flash Memory Programmer User’s Manual” and “Renesas Flash Programmer Flash memory programming software User’s Manual” for more details.
Page 830: Rom Area And Block Configuration
RX110 Group 31. Flash Memory 31.2 ROM Area and Block Configuration The maximum ROM size of this MCU is 128 Kbytes. The ROM area is divided into blocks. A block is 1-Kbyte area. When executing the block erase command, the memory is erased by the block. Figure 31.1 shows the ROM Area and Block Configuration.
Page 831 RX110 Group 31. Flash Memory Table 31.2 Correspondence Between ROM Capacity and Addresses for Reading ROM Capacity Addresses for Reading 16 Kbytes FFFF C000h to FFFF FFFFh 8 Kbytes FFFF E000h to FFFF FFFFh R01UH0421EJ0120 Rev.1.20 Page 831 of 968 Jul 29, 2016...
Page 832: Register Descriptions
RX110 Group 31. Flash Memory 31.3 Register Descriptions 31.3.1 Flash P/E Mode Entry Register (FENTRYR) Address(es): 007F FFB2h FENTR FEKEY[7:0] — — — — — — — Value after reset: Symbol Bit Name Description FENTRY0 ROM P/E Mode Entry 0 0: ROM is in read mode.
Page 833: Protection Unlock Register (Fpr)
RX110 Group 31. Flash Memory 31.3.2 Protection Unlock Register (FPR) Address(es): 007F C0C0h Value after reset: x: Undefined This write-only register is used to protect the FPMCR register from being rewritten inadvertently when the CPU runs out of control. Writing to the FPMCR register is enabled only when the following procedure is used to access the register. Procedure to unlock protection (1) Write A5h to the FPR register.
Page 834: Flash P/E Mode Control Register (Fpmcr)
RX110 Group 31. Flash Memory 31.3.4 Flash P/E Mode Control Register (FPMCR) Address(es): 007F FF80h FMS2 LVPE — FMS1 RPDIS — FMS0 — Value after reset: Symbol Bit Name Description — Reserved This bit is read as 0. The write value should be 0. FMS0 Flash Operating Mode Select 0 FMS2 FMS1 FMS0...
Page 835: Flash Initial Setting Register (Fisr)
RX110 Group 31. Flash Memory LVPE Bit (Low-Voltage P/E Mode Enable) Set this bit to 0 for programming/erasure in high-speed mode, and set this bit to 1 for programming/erasure in middle- speed mode. 31.3.5 Flash Initial Setting Register (FISR) Address(es): 007F C0B6h SAS[1:0] —...
Page 836 RX110 Group 31. Flash Memory Table 31.3 Example of FlashIF Clock Frequency Settings FlashIF Clock PCKA[4:0] Bit FlashIF Clock PCKA[4:0] Bit FlashIF Clock PCKA[4:0] Bit Frequency [MHz] Setting Frequency [MHz] Setting Frequency [MHz] Setting 01010b 01001b 01000b 00111b 00110b 00101b 00100b 00011b 00010b...
Page 837: Flash Reset Register (Fresetr)
RX110 Group 31. Flash Memory 31.3.6 Flash Reset Register (FRESETR) Address(es): 007F FF89h FRESE — — — — — — — Value after reset: Symbol Bit Name Description FRESET Flash Reset 0: Flash control circuit reset is released. 1: Flash control circuit is reset. b7 to b1 —...
Page 838: Flash Control Register (Fcr)
RX110 Group 31. Flash Memory 31.3.8 Flash Control Register (FCR) Address(es): 007F FF85h OPST STOP — CMD[3:0] Value after reset: Symbol Bit Name Description b3 to b0 CMD[3:0] Software Command Setting 0 0 0 1: Program 0 0 1 1: Blank check 0 1 0 0: Block erase 0 1 0 1: Unique ID read Settings other than above are prohibited.*...
Page 839: Flash Extra Area Control Register (Fexcr)
RX110 Group 31. Flash Memory sequencer ends the read cycle and enters the wait state. When issuing the unique ID read command again with this bit set to 0, the internal address of the sequencer is incremented by 4, and the next data is read. STOP Bit (Forced Processing Stop) This bit is used to forcibly stop the processing (blank check or block erase) being executed.
Page 840 RX110 Group 31. Flash Memory When registers FWBH and FWBL are set to values other than the above, do not execute the start-up area information program. [Access window information program] This command is used to set the access window used for area protection. Set the access window in block units.
Page 841: Flash Processing Start Address Register H (Fsarh)
RX110 Group 31. Flash Memory 31.3.10 Flash Processing Start Address Register H (FSARH) Address(es): 007F FF84h — — — — Value after reset: The FSARH register is used to set the target processing address or the start address of the target processing range in the flash memory when a software command is executed.
Page 842: Flash Processing End Address Register H (Fearh)
RX110 Group 31. Flash Memory 31.3.12 Flash Processing End Address Register H (FEARH) Address(es): 007F FF88h — — — — Value after reset: The FEARH register is used to set the end address of the target processing range in the flash memory when a software command is executed.
Page 843: Flash Read Buffer Register L (Frbl)
RX110 Group 31. Flash Memory 31.3.15 Flash Read Buffer Register L (FRBL) Address(es): 007F C0C2h Value after reset: This register is used to store the lower 2 bytes of the 4-byte data (part of the unique ID) that is read from the extra area when unique ID read is executed.
Page 844: Flash Status Register 0 (Fstatr0)
RX110 Group 31. Flash Memory 31.3.18 Flash Status Register 0 (FSTATR0) Address(es): 007F FF8Ah EILGLE ILGLER PRGER — — BCERR — ERERR Value after reset: Symbol Bit Name Description ERERR Erase Error Flag 0: Erasure terminates normally. 1: An error occurs during erasure. PRGERR Program Error Flag 0: Programming terminates normally.
Page 845 RX110 Group 31. Flash Memory [Clearing condition]  The next software command is executed. The value read from this flag is undefined when the FCR.STOP bit is set to 1 (processing is forcibly stopped) during blank checking. ILGLERR Flag (Illegal Command Error Flag) This flag indicates the result of executing a software command.
Page 846: Flash Status Register 1 (Fstatr1)
RX110 Group 31. Flash Memory 31.3.19 Flash Status Register 1 (FSTATR1) Address(es): 007F FF8Bh EXRDY FRDY — — — — DRRDY — Value after reset: Symbol Bit Name Description — Reserved This bit is read as 0. DRRDY Data Read Ready Flag 0: No valid data in registers FRBH and FRBL 1: Valid data in registers FRBH and FRBL —...
Page 847: Flash Error Address Monitor Register H (Feamh)
RX110 Group 31. Flash Memory 31.3.20 Flash Error Address Monitor Register H (FEAMH) Address(es): 007F C0BAh — — — — Value after reset: This register is used to check the address where the error has occurred if an error occurs during processing of a software command.
Page 848: Flash Start-Up Setting Monitor Register (Fscmr)
RX110 Group 31. Flash Memory 31.3.22 Flash Start-Up Setting Monitor Register (FSCMR) Address(es): 007F C0B0h — — — — — — — SASMF — — — — — — — — Value set by Value after reset: user* Symbol Bit Name Description b7 to b0 —...
Page 849: Flash Access Window End Address Monitor Register (Fawemr)
RX110 Group 31. Flash Memory 31.3.24 Flash Access Window End Address Monitor Register (FAWEMR) Address(es): 007F C0B4h — — — — — — Value after reset: The value set by the user* Note 1. The value of the blank product is 1. It is set to the same value set in bit 9 to bit 0 in the FWBH register after the access window information program command is executed.
Page 850: Start-Up Program Protection
RX110 Group 31. Flash Memory 31.4 Start-Up Program Protection When rewriting the start-up program * by self-programming, if the rewrite operation is interrupted due to temporary blackout, the start-up program may not be successfully programmed and the user program may not start properly. This problem can be avoided by rewriting the start-up program without erasing the existing start-up program using the start-up program protection.
Page 851: Area Protection
RX110 Group 31. Flash Memory 31.5 Area Protection Area protection enables rewriting only the selected blocks (access window) in the user area and disables rewriting the other blocks during self-programming. Specify the start address and end address to set the access window. While the access window can be set in boot mode or by self-programming, area protection is enabled only during self-programming in single-chip mode.
Page 852: Programming And Erasure
RX110 Group 31. Flash Memory 31.6 Programming and Erasure The ROM can be programmed and erased by changing the mode of the dedicated sequencer for programming and erasure, and by issuing commands for programming and erasure. The mode transitions and commands required to program or erase the ROM are described below. The descriptions apply in common to boot mode and single-chip mode.
Page 853: Mode Transitions
RX110 Group 31. Flash Memory 31.6.2 Mode Transitions 31.6.2.1 Transition from Read Mode to P/E Mode Switching to ROM P/E mode is required before executing a software command for the ROM. Figure 31.5 shows the Procedure for Transition from ROM Read Mode to ROM P/E Mode. Start in ROM read mode FENTRYR register = AA01h Set ROM P/E mode...
Page 854: Transition From P/E Mode To Read Mode
RX110 Group 31. Flash Memory 31.6.2.2 Transition from P/E Mode to Read Mode High-speed reading of the ROM requires switching to ROM read mode. Figure 31.6 shows the Procedure for Transition from ROM P/E Mode to ROM Read Mode. Start in ROM P/E mode FPR register = A5h Set 92h in FPMCR register = 92h...
Page 855: Software Commands
RX110 Group 31. Flash Memory 31.6.3 Software Commands Software commands consist of commands for programming and erasure and commands for programming start-up program area information and access window information. Table 31.4 lists the software commands for use with the flash memory.
Page 856: Software Command Usage
RX110 Group 31. Flash Memory 31.6.4 Software Command Usage This section describes how to use each software command, using flowcharts. 31.6.4.1 Program Figure 31.7 shows the procedure to issue the program command. Start in ROM P/E mode FASR.EXS bit = 0 Set programming address in registers FSARH and FSARL Set programming data in registers...
Page 857: Block Erase
RX110 Group 31. Flash Memory 31.6.4.2 Block Erase Figure 31.8 shows the procedure to issue the block erase command. Start in ROM P/E mode FASR.EXS bit = 0 Set the beginning address of the erasure block in registers FSARH and FSARL Set the last address of the erasure block in registers FEARH and FEARL FCR register = 84h...
Page 858: Blank Check
RX110 Group 31. Flash Memory 31.6.4.3 Blank Check Figure 31.9 shows the procedure to issue the blank check command. Start in ROM P/E mode FASR.EXS bit = 0 Set the blank check start address in registers FSARH and FSARL Set the blank check end address in registers FEARH and FEARL FCR register = 83h FSTATR1.FRDY flag = 1?
Page 859: Start-Up Area Information Program/Access Window Information Program
RX110 Group 31. Flash Memory 31.6.4.4 Start-Up Area Information Program/Access Window Information Program Figure 31.10 shows the procedure to issue the start-up area information program command and access window information program command. Start in ROM P/E mode FASR.EXS bit = 1 Set programming data in registers FWBH FWBL...
Page 860: Unique Id Read
RX110 Group 31. Flash Memory 31.6.4.5 Unique ID Read Figure 31.11 shows the procedure to issue the unique ID read command. Start in ROM P/E mode FASR.EXS bit = 1 FSARH register = 00h FSARL register = 0850h FEARH register = 00h FEARL register = 086Fh FCR register = 85h Issue the unique ID read command.
Page 861: Forced Stop Of Software Commands
RX110 Group 31. Flash Memory 31.6.4.6 Forced Stop of Software Commands Perform the procedure shown in Figure 31.12 to forcibly stop the blank check command or block erase command. When the command processing is forcibly stopped, registers FEAMH and FEAML store the address at the time of the forced stop.
Page 862 RX110 Group 31. Flash Memory 31.7 Boot Mode The SCI is used in boot mode. Table 31.6 lists the I/O Pins Used in Boot Mode. Table 31.5 Areas and Communication Functions Used in Boot Mode Boot Mode Item SCI Interface FINE Interface Programmable and erasable areas User area...
Page 863 RX110 Group 31. Flash Memory Reset circuit (User logic) RES# Data input TXD1 Data output RXD1 Note: A crystal or ceramic resonator is not required because the high-speed on-chip oscillator (HOCO) is used. Figure 31.13 Example of Pin Connections in Boot Mode (SCI) R01UH0421EJ0120 Rev.1.20 Page 863 of 968 Jul 29, 2016...
Page 864 RX110 Group 31. Flash Memory Table 31.7 Pin Handling in Boot Mode (SCI) Pin Name Name Function VCC, VSS Power supply — Input the guaranteed voltage for program/erase to the VCC pin. Input 0 V to the VSS pin. AVCC0, AVSS0 12-bit A/D converter power —...
Page 865 RX110 Group 31. Flash Memory 31.7.1.2 Starting Up in Boot Mode (SCI) To start up in boot mode (SCI), release the reset (drive the RES# pin high from low) while the MD pin is low. After starting up in boot mode (SCI), wait at least 400 ms until communication is enabled in boot mode (SCI). As shown in Figure 31.15 , keep the signal of each pin unchanged for 400 ms after the reset is released.
Page 866 RX110 Group 31. Flash Memory 31.7.2 Boot Mode (FINE Interface) The flash memory can be programmed and erased using the FINE in boot mode (FINE interface). The user area can be rewritten. Contact the manufacturer for details on the serial programmer. 31.7.2.1 Operating Conditions in Boot Mode (FINE Interface) FINE is used to communicate with the serial programmer in boot mode (FINE Interface).
Page 867 RX110 Group 31. Flash Memory 31.8 Flash Memory Access Disable Function The flash memory access disable function disables reading and programming of the flash memory. The boot mode ID code protection is for boot mode, and the on-chip debugging emulator ID code protection is for the on-chip debugging emulator.
Page 868 RX110 Group 31. Flash Memory 31.8.1.1 Boot Mode ID Code Protection Boot mode ID code protection disables reading and programming of the user area. When the control code indicates that the boot mode ID code protection is disabled while the user area is blank, the user area can be read and programmed.
Page 869 RX110 Group 31. Flash Memory Start Boot mode Protection enabled ID code protection enabled/disabled Protection disabled Matched Not blank Check received ID codes User area blank? Not matched/ retry ID codes do not match three times consecutively while Blank control code is 45h Erase-ready state Erase-ready state Sequence during normal processing...
Page 870 RX110 Group 31. Flash Memory 31.8.1.2 On-Chip Debugging Emulator ID Code Protection On-chip debugging emulator ID code protection enables or disables connection with the on-chip debugging emulator. When the on-chip debugging emulator ID code protection is disabled, connection with the on-chip debugging emulator is enabled.
Page 871 RX110 Group 31. Flash Memory 31.9 Communication Protocol This section describes the protocol used in boot mode. When developing a serial programmer, control with this communication protocol. 31.9.1 State Transition in Boot Mode (SCI) Figure 31.19 shows the Boot Mode (SCI) State Transition. Descriptions for numbers in parenthesis are on the following page.
Page 872 RX110 Group 31. Flash Memory (1) Bit rate automatic adjustment state In this state, the bit rate is automatically adjusted for communication with the host. When the bit rate adjustment is completed, the MCU sends 00h to the host. After that, when the MCU receives 55h sent from the host, the MCU sends E6h to the host, and the MCU enters the inquiry/setting host command wait state.
Page 873 RX110 Group 31. Flash Memory 31.9.3 Boot Mode Status Inquiry This command is used to check the current state and the previous error of the boot program. The MCU returns a code from Table 31.12 and Table 31.13 as the current state and the previous error. The boot mode status inquiry command can be used in the inquiry/setting host command wait state and program/erase state.
Page 874 RX110 Group 31. Flash Memory 31.9.4 Inquiry Commands Inquiry commands are used to obtain necessary information for sending setting commands, program/erase commands, and read-check commands. Table 31.14 lists the inquiry commands. These commands can only be used in the inquiry/setting host command wait state. Table 31.14 Inquiry Commands Command...
Page 875 RX110 Group 31. Flash Memory 31.9.4.3 User Area Information Inquiry When the host sends this command, the MCU sends the number of user areas and addresses. Command Number of Response Size areas Area start address Area end address Size (1 byte): Total bytes of Number of areas, Area start address, and Area end address (the value is always 09h) Number of areas (1 byte): Number of user areas (the value is always 01h) Area start address (4 bytes): Start address of the user area Area end address (4 bytes): End address of the user area...
Page 876 RX110 Group 31. Flash Memory 31.9.5 Setting Commands Setting commands are used to configure the settings necessary to execute program/erase commands in the MCU. Table 31.15 lists Setting Commands. These commands can be used only in the inquiry/setting host command wait state. Table 31.15 Setting Commands Command...
Page 877 RX110 Group 31. Flash Memory 31.9.5.2 Operating Frequency Select When the host sends a command to set the bit rate, select 16 MHz input clock and a bit rate with error of less than 4%. When the settings are supported, the MCU sends a response. When the settings are not supported or the transmitted command is invalid, the MCU sends an error response.
Page 878 RX110 Group 31. Flash Memory 31.9.5.3 Program/Erase State Transition When the host sends this command, the MCU determines whether boot mode ID code protection is enabled or disabled. When boot mode ID code protection is disabled while the user area is blank, the MCU sends a response (06h) indicating that ID code protection is disabled and the MCU enters the program/erase state.
Page 879 RX110 Group 31. Flash Memory 31.9.6 ID Code Authentication Command The ID code authentication command is used to send data from the host to compare with the control code and ID code 1 to ID code 15 on the ROM when the boot mode ID code protection is enabled. Table 31.16 lists ID code authentication command.
Page 880 RX110 Group 31. Flash Memory 31.9.6.2 Erase Ready The erase ready is a part of the boot mode ID code protection to disable reading data stored in the user area when protection is disabled while the user area is not blank or when ID codes do not match three times while the control code is 45h.
Page 881 RX110 Group 31. Flash Memory 31.9.7.1 User Area Program Preparation When the host sends this command, the MCU recognizes that an instruction to prepare for the program command is issued from the host, enters the program wait state, where only the program command to the user area can be accepted, and sends a response.
Page 882 RX110 Group 31. Flash Memory 31.9.7.3 Erase Preparation When the host sends this command, the MCU recognizes that an instruction to prepare for the erase command is issued from the host, enters the erase wait state, where only the block erase command to the user area can be accepted, and sends a response.
Page 883 RX110 Group 31. Flash Memory 31.9.8 Read-Check Commands Read-check commands are used to read or check the user area in the MCU based on the response to inquiry commands. Table 31.20 lists read-check commands used in the program/erase command wait state. Table 31.20 Read-Check Commands Command...
Page 884 RX110 Group 31. Flash Memory Error response Error Error (1 byte): Error code 11h: SUM error 2Ah: Address error  A value other than 01h is set for the “Area” field.  The read start address is not in the selected area. 2Bh: Size error ...
Page 885 RX110 Group 31. Flash Memory 31.9.8.4 Access Window Information Program For the access window start address sent from the host, set the block start address of the user area. For the access window end address, set the block end address of the user area. When the specified access window settings are successfully completed, the MCU sends a response.
Page 886 RX110 Group 31. Flash Memory 31.9.8.5 Access Window Read Send command 73h 01h FFh 8Dh from the host. When the MCU successfully reads the access window settings, the MCU sends the access window start address and end address that the MCU read. If the SUM of the received command does not match, the MCU sends an error response.
Page 887 RX110 Group 31. Flash Memory 31.9.9 Serial Programmer Operation in Boot Mode (SCI) The following describes the procedure for the serial programmer to program/erase the user area in boot mode (SCI). 1. Automatically adjust the bit rate 2. Receive the MCU information * 3.
Page 888 RX110 Group 31. Flash Memory 31.9.9.1 Bit Rate Automatic Adjustment Procedure The MCU measures the low width of data 00h that is sent from the serial programmer at 9,600 or 19,200 bps to automatically adjust the bit rate. At least 1 ms between commands Transmission to the MCU...
Page 889 RX110 Group 31. Flash Memory 31.9.9.2 Procedure to Receive the MCU Information Send inquiry commands, and receive the information necessary to send setting commands, program/erase commands, and read-check commands. (1) Send a support device inquiry command (20h) to check which device to connect. The MCU returns the device code and series name.
Page 890 RX110 Group 31. Flash Memory 31.9.9.3 Procedure to Select the Device and Change the Bit Rate Set the device to connect with the programmer and change the bit rate for communication. (1) Send the device select command (10h) to select the device to connect with the programmer and the endian of data that is programmed.
Page 891 RX110 Group 31. Flash Memory 31.9.9.4 Transition to the Program/Erase State The MCU needs to enter the program/erase state to perform program/erase operations. Send the program/erase state transition command (40h). The MCU responds according to ID codes and the state of the user area.
Page 892 RX110 Group 31. Flash Memory 31.9.9.5 Unlock Boot Mode ID Code Protection After the MCU is connected with the programmer, the boot mode ID code protection is enabled so program/read, and read-check operations cannot be performed. Disable this boot mode ID code protection. Send the ID code check command (60h).
Page 893 RX110 Group 31. Flash Memory 31.9.9.6 Erase Ready Operation Erase the user area in the MCU. (1) Send the erase preparation command (48h) to place the MCU in the erase wait state. The MCU enters the erase wait state and sends a response (06h). (2) Send a block erase command (59h) to erase blocks in the MCU.
Page 894 RX110 Group 31. Flash Memory 31.9.9.7 Erase the User Area Erase blocks that are programmed in the user area to program a user program. (1) Send an erase preparation command (48h) to place the MCU in the erase wait state. The MCU enters the erase wait state and sends a response (06h).
Page 895 RX110 Group 31. Flash Memory 31.9.9.8 Program the User Area Program a user program in the user area. (1) Send the user program preparation command (43h) to place the MCU in the program wait state. The MCU enters the program wait sate and sends a response (06h). (2) Send the program command (50h).
Page 896 RX110 Group 31. Flash Memory 31.9.9.9 Check Data in the User Area Read and check, checksum, and blank check the user area to check the programmed data in the user area. (1) The read and check operation is used to read data in the user area and compare the read data with the programmed data to check if the program operation is performed successfully.
Page 897 RX110 Group 31. Flash Memory 31.9.9.10 Set the Access Window in the User Area Set the access window to avoid unintentionally rewriting the user area during the self-programming. (1) Send the access window program command (74h) to set the access window or clear the access window settings. When setting the access window, set 00h in the access window field, and set the start address and the end address of the area that can be programmed during self-programming in the access window start address and the access window end address, respectively.
Page 898 RX110 Group 31. Flash Memory 31.10 Rewriting by Self-Programming 31.10.1 Overview The MCU supports rewriting of the flash memory by the user program. The ROM can be rewritten by preparing a routine to rewrite the flash memory (flash rewrite routine) in the user program. On-chip RAM Flash rewrite routine Erase/program...
Page 899 RX110 Group 31. Flash Memory 31.11 Usage Notes (1) Access the Block Where Erase Operation is Forcibly Stopped When forcibly stopping an erase operation, data in the block where the erase operation is aborted is undefined. To avoid malfunctions caused by reading undefined data, do not execute instructions or read data in the block where an erase operation is forcibly stopped.
Page 900 RX110 Group 31. Flash Memory 31.12 Usage Notes in Boot Mode (1) Notes on Communication Errors in Boot Mode When communication with the MCU cannot be performed properly, reset and start up in boot mode again. (2) Notes on Power Supply Voltage in Boot Mode (SCI) When the bit rate exceeds 500 kbps in boot mode (SCI), use a voltage that is 3.0 V or higher.
Page 901 RX110 Group 32. Electrical Characteristics Electrical Characteristics 32.1 Absolute Maximum Ratings Table 32.1 Absolute Maximum Ratings Conditions: VSS = AVSS0 = VREFL0 = 0 V Item Symbol Value Unit Power supply voltage –0.3 to +4.6 Input voltage Ports for 5 V tolerant* –0.3 to +6.5 Ports P40 to P44, P46, –0.3 to AVCC0 +0.3...
Page 902 RX110 Group 32. Electrical Characteristics 32.2 DC Characteristics Table 32.3 DC Characteristics (1) Conditions: 2.7 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Test Item Symbol Min.
Page 903 RX110 Group 32. Electrical Characteristics Table 32.4 DC Characteristics (2) Conditions: 1.8 V ≤ VCC < 2.7 V, 1.8 V ≤ AVCC0 < 2.7 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Test Item Symbol Min. Typ.
Page 904 RX110 Group 32. Electrical Characteristics Table 32.7 DC Characteristics (5) (1/2) 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T Conditions: = –40 to +105°C Test Item Symbol Unit Conditions Supply...
Page 905 RX110 Group 32. Electrical Characteristics Table 32.7 DC Characteristics (5) (2/2) 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T Conditions: = –40 to +105°C Test Item Symbol Unit Conditions μA...
Page 906 RX110 Group 32. Electrical Characteristics = 85/105°C, ICLK = 12 MHz = 85/105°C, ICLK = 8 MHz = 25°C, ICLK = 12 MHz = 25°C, ICLK = 8 MHz = 85/105°C, ICLK = 1 MHz = 25°C, ICLK = 1 MHz VCC (V) Note 1.
Page 907 RX110 Group 32. Electrical Characteristics Table 32.8 DC Characteristics (6) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Item Symbol Typ.* Max. Unit Test Conditions μA...
Page 908 = -40 to 105°C)* Note 1. Total power dissipated by the entire chip (including output currents). Note 2. Please contact Renesas Electronics sales office for derating under T = +85°C to 105°C. Derating is the systematic reduction of load for the sake of improved reliability.
Page 909 RX110 Group 32. Electrical Characteristics Table 32.10 DC Characteristics (8) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Test Item Symbol Min. Typ.
Page 910 RX110 Group 32. Electrical Characteristics r(VCC) r(VCC) Figure 32.6 Ripple Waveform Table 32.14 DC Characteristics (12) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Item Symbol Min.
Page 911 RX110 Group 32. Electrical Characteristics Table 32.16 Permissible Output Currents (2) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, = –40 to +105°C (G version) Item Symbol Max.
Page 912 RX110 Group 32. Electrical Characteristics Table 32.17 Output Voltage (1) 2.7 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T Conditions: = –40 to +10°C Item Symbol Min. Max. Unit Test Conditions Low-level...
Page 913 RX110 Group 32. Electrical Characteristics 32.2.1 Standard I/O Pin Output Characteristics (1) Figure 32.7 to Figure 32.10 show the characteristics of general ports (except for the RIIC output pin, ports P40 to P44, P46, ports PJ6, PJ7). vs V VCC = 3.3 V VCC = 2.7 V VCC = 1.8 V VCC = 1.8 V...
Page 914 RX110 Group 32. Electrical Characteristics vs V °C = –40 = 25°C = 105°C – = 105°C – = 25°C – °C = –40 – Figure 32.9 and I Temperature Characteristics of General Ports (Except for the RIIC Output Pin, Ports P40 to P44, P46, Ports PJ6, PJ7) at VCC = 2.7 V (Reference Data) vs V 40°C –...
Page 915 RX110 Group 32. Electrical Characteristics 32.2.2 Standard I/O Pin Output Characteristics (2) Figure 32.11 to Figure 32.13 show the characteristics of the RIIC output pin. vs V VCC = 3.3 V VCC = 2.7 V Figure 32.11 V and I Voltage Characteristics of RIIC Output Pin at T = 25°C (Reference Data) vs V...
Page 916 RX110 Group 32. Electrical Characteristics vs V 40°C – = 25°C = 105°C Figure 32.13 V and I Temperature Characteristics of RIIC Output Pin at VCC = 3.3 V (Reference Data) R01UH0421EJ0120 Rev.1.20 Page 916 of 968 Jul 29, 2016...
Page 917 RX110 Group 32. Electrical Characteristics 32.2.3 Standard I/O Pin Output Characteristics (3) Figure 32.14 to Figure 32.17 show the characteristics ports P40 to P44, P46, ports PJ6, PJ7. vs V VCC = 3.3 V VCC = 2.7 V VCC = 1.8 V VCC = 1.8 V –...
Page 918 RX110 Group 32. Electrical Characteristics vs V 40°C – = 25°C = 105°C = 105°C –2 = 25°C 40°C – –4 Figure 32.16 V and I Temperature Characteristics of Ports P40 to P44, P46, Ports PJ6, PJ7 at VCC = 2.7 V (Reference Data) vs V 40°C –...
Page 919 RX110 Group 32. Electrical Characteristics 32.3 AC Characteristics 32.3.1 Clock Timing Table 32.19 Operation Frequency Value (High-Speed Operating Mode) 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T Conditions: = –40 to +105°C Item...
Page 920 RX110 Group 32. Electrical Characteristics Table 32.22 Clock Timing Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Item Symbol Min. Typ. Max. Unit Test Conditions XTAL external clock input cycle time...
Page 921 RX110 Group 32. Electrical Characteristics ILOCOCR.ILCSTP ILOCO IWDT-dedicated clock oscillator output Figure 32.19 IWDT-Dedicated Clock Oscillation Start Timing MOSCCR.MOSTP MAINOSC Main clock oscillator output Figure 32.20 Main Clock Oscillation Start Timing LOCOCR.LCSTP LOCO LOCO clock oscillator output Figure 32.21 LOCO Clock Oscillation Start Timing RES# Internal reset RESWT...
Page 922 RX110 Group 32. Electrical Characteristics HOCOCR.HCSTP HOCO HOCO clock Figure 32.23 HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting HOCOCR.HCSTP Bit) SOSCCR.SOSTP SUBOSC Sub-clock oscillator output Figure 32.24 Sub-Clock Oscillation Start Timing R01UH0421EJ0120 Rev.1.20 Page 922 of 968 Jul 29, 2016...
Page 923 RX110 Group 32. Electrical Characteristics 32.3.2 Reset Timing Table 32.23 Reset Timing Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Item Symbol Min.
Page 924 RX110 Group 32. Electrical Characteristics 32.3.3 Timing of Recovery from Low Power Consumption Modes Table 32.24 Timing of Recovery from Low Power Consumption Modes (1) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Test Item...
Page 925 RX110 Group 32. Electrical Characteristics Table 32.26 Timing of Recovery from Low Power Consumption Modes (3) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Test Item Symbol...
Page 926 RX110 Group 32. Electrical Characteristics Table 32.27 Timing of Recovery from Low Power Consumption Modes (4) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Item Symbol Min.
Page 927 RX110 Group 32. Electrical Characteristics 32.3.4 Control Signal Timing Table 32.29 Control Signal Timing Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Item Symbol Min.
Page 928 RX110 Group 32. Electrical Characteristics 32.3.5 Timing of On-Chip Peripheral Modules Table 32.30 Timing of On-Chip Peripheral Modules (1) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Test Item...
Page 929 RX110 Group 32. Electrical Characteristics Table 32.31 Timing of On-Chip Peripheral Modules (2) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C, C = 30 pF Item Symbol Min.
Page 930 RX110 Group 32. Electrical Characteristics Table 32.32 Timing of On-Chip Peripheral Modules (3) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C, C = 30 pF Item Symbol Min.
Page 931 RX110 Group 32. Electrical Characteristics Table 32.33 Timing of On-Chip Peripheral Modules (4) Conditions: 2.7 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, fPCLKB ≤ 32 MHz, T = –40 to +105°C Item Symbol Min.*...
Page 932 RX110 Group 32. Electrical Characteristics Table 32.34 Timing of On-Chip Peripheral Modules (5) Conditions: 2.7 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, fPCLKB ≤ 32 MHz, T = –40 to +105°C Item Symbol Min.
Page 933 RX110 Group 32. Electrical Characteristics PCLK MTCLKA to MTCLKH TCKWL TCKWH Figure 32.34 MTU2 Clock Input Timing SCKW SCKr SCKf SCKn (n = 1, 5, 12) Scyc Figure 32.35 SCK Clock Input Timing SCKn TXDn RXDn (n = 1, 5, 12) Figure 32.36 SCI Input/Output Timing: Clock Synchronous Mode R01UH0421EJ0120 Rev.1.20 Page 933 of 968...
Page 934 RX110 Group 32. Electrical Characteristics PCLK ADTRG0# TRGW Figure 32.37 A/D Converter External Trigger Input Timing Ccyc CLKOUT pin output Test conditions: V = VCC × 0.7, V = VCC × 0.3, I = -1.0 mA, I = 1.0 mA, C = 30 pF Figure 32.38 CLKOUT Output Timing SPCKr SPCKf...
Page 935 RX110 Group 32. Electrical Characteristics RSPI Simple SPI SSLA0 to SSLA3 output LEAD SSLr, SSLf RSPCKA SCKn CPOL = 0 CKPOL = 0 output output RSPCKA SCKn CPOL = 1 CKPOL = 1 output output MISOA SMISOn MSB IN DATA LSB IN MSB IN input...
Page 936 RX110 Group 32. Electrical Characteristics RSPI Simple SPI SSLA0 to SSLA3 output LEAD SSLr, SSLf RSPCKA SCKn CPOL = 0 CKPOL = 1 output output RSPCKA SCKn CPOL = 1 CKPOL = 0 output output MISOA SMISOn MSB IN DATA LSB IN MSB IN input...
Page 937 RX110 Group 32. Electrical Characteristics RSPI Simple SPI SSLA0 SSn# input input LEAD RSPCKA SCKn CPOL = 0 CKPOL = 0 input input RSPCKA SCKn CPOL = 1 CKPOL = 1 input input MISOA SMISOn MSB OUT DATA LSB OUT MSB IN MSB OUT output...
Page 938 RX110 Group 32. Electrical Characteristics SDA0 SCLH STAH STAS STOS SCL0 SCLL SDAS SDAH Test conditions Note 1. S, P, and Sr indicate the following conditions, respectively. = VCC × 0.7, V = VCC × 0.3 S: START condition P: STOP condition Sr: Repeated START condition Figure 32.46 RIIC Bus Interface Input/Output Timing and Simple I C Bus Interface Input/Output...
Page 939 RX110 Group 32. Electrical Characteristics 32.4 A/D Conversion Characteristics Table 32.35 A/D Conversion Characteristics (1) Conditions: 2.7 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = VREFL0 = 0 V, = –40 to +105°C Item Min.
Page 940 RX110 Group 32. Electrical Characteristics AVREFH0 Characteristics listed in Table 32.35 A/D Conversion Characteristics (1) Characteristics listed in Table 32.36 A/D Conversion Characteristics (2) Characteristics listed in Table 32.37 A/D Conversion Characteristics (3) 2.4 2.7 AVCC0 Figure 32.47 AVCC0 to AVREFH Voltage Range R01UH0421EJ0120 Rev.1.20 Page 940 of 968 Jul 29, 2016...
Page 941 RX110 Group 32. Electrical Characteristics Table 32.36 A/D Conversion Characteristics (2) Conditions: 2.4 V ≤ VCC ≤ 3.6 V, 2.4 V ≤ AVCC0 ≤ 3.6 V, 2.4 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = VREFL0 = 0 V, = –40 to +105°C Item Min.
Page 942 RX110 Group 32. Electrical Characteristics Table 32.38 A/D Converter Channel Classification Classification Channel Conditions Remarks High-precision channel AN000 to AN004, AN006 AVCC0 = 1.8 to 3.6 V Pins AN000 to AN004 and AN006 cannot be used as digital outputs when Normal-precision channel AN008 to AN015 the A/D converter is in use.
Page 943 RX110 Group 32. Electrical Characteristics FFFh Full-scale error Integral nonlinearity error (INL) A/D converter output code Ideal line of actual A/D conversion characteristic Actual A/D conversion characteristic Ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D...
Page 944 RX110 Group 32. Electrical Characteristics Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics and the width of the actually output code. Offset error Offset error is the difference between a transition point of the ideal first output code and the actual first output code. Full-scale error Full-scale error is the difference between a transition point of the ideal last output code and the actual last output code.
Page 945 RX110 Group 32. Electrical Characteristics 32.6 Power-On Reset Circuit and Voltage Detection Circuit Characteristics Table 32.41 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (1) Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Item Symbol...
Page 946 RX110 Group 32. Electrical Characteristics VOFF 1.0 V Internal reset signal (active-low) Figure 32.49 Voltage Detection Reset Timing 1.0 V w(POR) Internal reset signal (active-low) Note 1. t is the time required for a power-on reset to be enabled while the external power VCC is being held below the w(por) valid voltage (1.0 V).
Page 947 RX110 Group 32. Electrical Characteristics VOFF det1 LVD1E d(E-A) LVD1 Comparator output LVD1CMPE LVD1MON Internal reset signal (active-low) When LVD1RN = L LVD1 When LVD1RN = H LVD1 Figure 32.51 Voltage Detection Circuit Timing (V det1 VOFF det2 LVD2E d(E-A) LVD2 Comparator output LVD2CMPE...
Page 948 RX110 Group 32. Electrical Characteristics 32.7 Oscillation Stop Detection Timing Table 32.43 Oscillation Stop Detection Circuit Characteristics Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T = –40 to +105°C Test Item Symbol...
Page 949 However, programming the same address for several times as one erasing is not enabled (overwriting is prohibited). Note 2. Characteristic when using the flash memory programmer and the self-programming library provided from Renesas Electronics. Note 3. This result is obtained from reliability testing.
Page 950 RX110 Group 32. Electrical Characteristics Table 32.46 ROM (Flash Memory for Code Storage) Characteristics (3) Middle-speed operating mode Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V Temperature range for the programming/erasure operation: T = –40 to +85°C FCLK = 1 MHz FCLK = 8 MHz...
Page 951 For the capacitors related to analog modules, also see section 27, 12-Bit A/D Converter (S12ADb) . For notes on designing the printed circuit board, see the descriptions of the application note "Hardware Design Guide" (R01AN1411EJ). The latest version can be downloaded from Renesas Electronics Website. Bypass capacitor 0.1 µF...
Page 952 RX110 Group 32. Electrical Characteristics Bypass capacitor 0.1 µF RX110 Group PLQP0048KB-A (48-pin LFQFP) (Top view) AVSS0 Bypass capacitor 0.1 µF AVCC0 Bypass Bypass capacitor capacitor 4.7 µF 0.1 µF Note. Do not apply the power supply voltage to the VCL pin. Use a 4.7-µF multilayer ceramic for the VCL pin and place it close to the pin.
Page 953 RX110 Group Appendix 1. Port States in Each Processing Mode Appendix 1. Port States in Each Processing Mode Table 1.1 Port States in Each Processing State Port Name (Pin Name) Reset Software Standby Mode Hi-Z Keep-O Hi-Z Keep-O P14 (IRQ4) Hi-Z Keep-O* P15 (IRQ5/CLKOUT)
Page 954 RX110 Group Appendix 2. Package Dimensions Appendix 2. Package Dimensions Information on the latest version of the package dimensions or mountings has been displayed in “Packages” on Renesas Electronics Corporation website. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LFQFP64-10x10-0.50...
Page 955 RX110 Group Appendix 2. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] 64P6U-A/ ⎯ P-LQFP64-14x14-0.80 PLQP0064GA-A 0.7g NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters...
Page 956 (APERTURE OF 0.75 0.75 0.75 SOLDER RESIST) 0.75 0.55 0.04 R0.35 0.015 0.55 0.04 P64FC-50-AN5 0.70 0.03 0.70 0.03 2011 Renesas Electronics Corporation. All rights reserved. Figure C 64-Pin WFLGA (PWLG0064KA-A) R01UH0421EJ0120 Rev.1.20 Page 956 of 968 Jul 29, 2016...
Page 957 RX110 Group Appendix 2. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LFQFP48-7x7-0.50 PLQP0048KB-A 48P6Q-A 0.2g NOTE) 1. DIMENSIONS " 1" AND " 2" DO NOT INCLUDE MOLD FLASH. DIMENSION " 3" DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters...
Page 958 0.05 0.05 ITEM MIN NOM MAX MIN NOM MAX EXPOSED 5.45 5.50 5.55 5.45 5.50 5.55 DIE PAD VARIATIONS 2012 Renesas Electronics Corporation. All rights reserved. Figure E 48-Pin HWQFN (PWQN0048KB-A) R01UH0421EJ0120 Rev.1.20 Page 958 of 968 Jul 29, 2016...
Page 959 0.05 0.05 ITEM MIN NOM MAX MIN NOM MAX EXPOSED 4.45 4.50 4.55 4.45 4.50 4.55 DIE PAD VARIATIONS 2012 Renesas Electronics Corporation. All rights reserved. Figure F 40-Pin HWQFN (PWQN0040KC-A) R01UH0421EJ0120 Rev.1.20 Page 959 of 968 Jul 29, 2016...
Page 960 0.34±0.05 0.20 0.55 0.55 R0.275±0.05 (APERTURE OF 0.75 SOLDER RESIST) 0.75 0.75 0.75 0.55±0.05 0.55±0.05 R0.35±0.05 0.70± 0.05 0.70±0.05 2012 Renesas Electronics Corporation. All rights reserved. Figure G 36-Pin WFLGA (PWLG0036KA-A) R01UH0421EJ0120 Rev.1.20 Page 960 of 968 Jul 29, 2016...
Page 961 REVISION HISTORY RX110 Group REVISION HISTORY REVISION HISTORY RX110 Group User’s Manual: Hardware Classifications - Items with Technical Update document number: Changes according to the corresponding issued Technical Update - Items without Technical Update document number: Minor changes that do not require Technical Update to be issued Description Rev.
Page 962 RX110 Group REVISION HISTORY Description Rev. Date Classification Page Summary 1.10 Dec 10, 2014 22. Independent Watchdog Timer (IWDTa) 22. Independent Watchdog Timer (IWDTa): PCLKB description added 22.3.3 Refresh Operation: [Sample refreshing timings] changed Figure 22.6 IWDT Refresh Operation Waveforms (IWDTCR.CKS[3:0] = 0000b, IWDTCR.TOPS[1:0] = 11b), changed 22.3.8 Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers, changed...
Page 963 RX110 Group REVISION HISTORY Description Rev. Date Classification Page Summary 1.10 Dec 10, 2014 31.3.13 Flash Processing End Address Register L (FEARL), changed 31.3.14 Flash Read Buffer Register H (FRBH) and 31.3.15 Flash Read TN-RX*-A113A/E Buffer Register L (FRBL), changed 855, 856 31.3.18 Flash Status Register 0 (FSTATR0): Bit function table, PRGERR flag TN-RX*-A112A/E...
Page 964 RX110 Group REVISION HISTORY Description Rev. Date Classification Page Summary 1.10 Dec 10, 2014 Figure 31.19 Transmit/Receive Data for Bit Rate Automatic Adjustment, TN-RX*-A112A/E changed 31.9.9.2 Procedure to Receive the MCU Information and Figure 31.21 TN-RX*-A112A/E Procedure to Send Inquiry Commands, changed 31.9.9.3 Procedure to Select the Device and Change the Bit Rate and Figure TN-RX*-A112A/E 31.22 Procedure to Select the Device and Change the Bit Rate, changed...
Page 965 RX110 Group REVISION HISTORY Description Rev. Date Classification Page Summary 1.20 2016.07.29 23. Serial Communications Interface (SCIe, SCIf) Figure 23.1 Block Diagram of SCIe (SCI1), deleted title changed Figure 23.2 Block Diagram of SCIe (SCI5) → Figure 23.1 Block Diagram of SCIe (SCI1 and SCI5) 23.2.5 Serial Mode Register (SMR) (1) Non-Smart Card Interface Mode (SCMR.SMIF = 0) b7 changed...
Page 966 Colophon RX110 Group User’s Manual: Hardware Publication Date: Rev.1.00 Dec 20, 2013 Rev.1.20 Jul 29, 2016 Published by: Renesas Electronics Corporation...
Page 967 SALES OFFICES SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. Renesas Electronics America Inc. 2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A.
Page 968 Back cover RX110 Group R01UH0421EJ0120...

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