ST STM32L4 5 Series Reference Manual page 1331

RM0351
40.5.12 USART Single-wire Half-duplex communication
Single-wire Half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:
•
LINEN and CLKEN bits in the USART_CR2 register,
•
SCEN and IREN bits in the USART_CR3 register.
The USART can be configured to follow a Single-wire Half-duplex protocol where the TX
and RX lines are internally connected. The selection between half- and Full-duplex
communication is made with a control bit HDSEL in USART_CR3.
As soon as HDSEL is written to 1:
•
The TX and RX lines are internally connected
•
The RX pin is no longer used
•
The TX pin is always released when no data is transmitted. Thus, it acts as a standard
I/O in idle or in reception. It means that the I/O must be configured so that TX is
configured as alternate function open-drain with an external pull-up.
Apart from this, the communication protocol is similar to normal USART mode. Any conflicts
on the line must be managed by software (by the use of a centralized arbiter, for instance).
In particular, the transmission is never blocked by hardware and continues as soon as data
is written in the data register while the TE bit is set.
40.5.13 USART Smartcard mode
This section is relevant only when Smartcard mode is supported. Please refer to
Section 40.4: USART implementation on page
Smartcard mode is selected by setting the SCEN bit in the USART_CR3 register. In
Smartcard mode, the following bits must be kept cleared:
•
LINEN bit in the USART_CR2 register,
•
HDSEL and IREN bits in the USART_CR3 register.
Moreover, the CLKEN bit may be set in order to provide a clock to the smartcard.
The smartcard interface is designed to support asynchronous protocol for smartcards as
defined in the ISO 7816-3 standard. Both T=0 (character mode) and T=1 (block mode) are
supported.
The USART should be configured as:
•
8 bits plus parity: where word length is set to 8 bits and PCE=1 in the USART_CR1
register
•
1.5 stop bits when transmitting and receiving data: where STOP=11 in the
USART_CR2 register. It is also possible to choose 0.5 stop bit for receiving.
In T=0 (character) mode, the parity error is indicated at the end of each character during the
guard time period.
Figure 421
error.
Universal synchronous asynchronous receiver transmitter (USART)
shows examples of what can be seen on the data line with and without parity
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