Table 230. I2C Interrupt Requests - ST STM32L4 5 Series Reference Manual

Inter-integrated circuit (I2C) interface
Receive buffer not empty
Transmit buffer interrupt status
Stop detection interrupt flag
Transfer Complete Reload
Transfer complete
Address matched
NACK reception
Bus error
Arbitration loss
Overrun/Underrun
PEC error
Timeout/t
SMBus Alert
Depending on the product implementation, all these interrupts events can either share the
same interrupt vector (I2C global interrupt), or be grouped into 2 interrupt vectors (I2C event
interrupt and I2C error interrupt). Refer to
details.
In order to enable the I2C interrupts, the following sequence is required:
1. Configure and enable the I2C IRQ channel in the NVIC.
2. Configure the I2C to generate interrupts.
The I2C wakeup event is connected to the EXTI controller (refer to
interrupts and events controller
1284/1830

Table 230. I2C Interrupt requests

Interrupt event
error
LOW
DocID024597 Rev 5
Event flag/Interrupt
Event flag
RXNE
TXIS
STOPF
TCR
TC
ADDR
NACKF
BERR
ARLO
OVR
PECERR Write PECERRCF=1
TIMEOUT Write TIMEOUTCF=1
ALERT
Table 57: STM32L4x5/STM32L4x6 vector table
(EXTI)).
Interrupt enable
clearing method
Read I2C_RXDR
register
Write I2C_TXDR
register
Write STOPCF=1
Write I2C_CR2 with
NBYTES[7:0] ≠ 0
Write START=1 or
STOP=1
Write ADDRCF=1
Write NACKCF=1
Write BERRCF=1
Write ARLOCF=1
Write OVRCF=1
Write ALERTCF=1
Section 14: Extended
RM0351
control bit
RXIE
TXIE
STOPIE
TCIE
ADDRIE
NACKIE
ERRIE
for