ST STM32L4 5 Series Reference Manual page 1346

Universal synchronous asynchronous receiver transmitter (USART)
40.8 USART registers
Refer to
40.8.1 Control register 1 (USART_CR1)
Address offset: 0x00
Reset value: 0x0000
31 30 29
Res. Res. Res.
15 14 13
OVER8 CMIE MME
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Bits 31:29 Reserved, must be kept at reset value
Bit 28 M1: Word length
This bit, with bit 12 (M0), determines the word length. It is set or cleared by software.
M[1:0] = 00: 1 Start bit, 8 data bits, n stop bits
M[1:0] = 01: 1 Start bit, 9 data bits, n stop bits
M[1:0] = 10: 1 Start bit, 7 data bits, n stop bits
This bit can only be written when the USART is disabled (UE=0).
Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Auto baud rate
Bit 27 EOBIE: End of Block interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated when the EOBF flag is set in the USART_ISR register
Note: If the USART does not support Smartcard mode, this bit is reserved and forced by
Bit 26 RTOIE: Receiver timeout interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated when the RTOF bit is set in the USART_ISR register.
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
Bits 25:21 DEAT[4:0]: Driver Enable assertion time
This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and
the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit duration,
depending on the oversampling rate).
This bit field can only be written when the USART is disabled (UE=0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept
1346/1830
Section 1.1 on page 67
28 27 26 25
M1 EOBIE RTOIE
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12 11 10 9
M0 WAKE PCE PS
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(0x7F and 0x55 frames detection) are not supported.
hardware to '0'. Please refer to
forced by hardware to '0'.
cleared. Please refer to
for a list of abbreviations used in register descriptions.
24 23 22
DEAT[4:0]
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8 7 6
PEIE TXEIE TCIE
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Section 40.4: USART implementation on page
Section 40.4: USART implementation on page
Section 40.4: USART implementation on page
DocID024597 Rev 5
21 20 19
DEDT[4:0]
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5 4 3
RXNEIE IDLEIE TE
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RM0351
18 17 16
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2 1 0
RE UESM UE
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1304.
1304.
1304.