Xilinx Virtex-5 FPGA User Manual page 341

X-Ref Target - Figure 7-18
Figure 7-18: Instantiate IDELAYCTRL Without LOC Constraints - RDY Unconnected
2.
X-Ref Target - Figure 7-19
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
REFCLK
RST
. .
. .
. .
When RDY port is connected, an AND gate of width equal to the number of clock
regions is instantiated and the RDY output ports from the instantiated and replicated
IDELAYCTRL instances are connected to the inputs of the AND gate. The tools assign
the signal name connected to the RDY port of the instantiated IDELAYCTRL instance
to the output of the AND gate.
The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive
without LOC constraints with the RDY port connected are provided in the Libraries
Guide.
The resulting circuitry after instantiating the IDELAYCTRL components is illustrated
in Figure 7-19.
REFCLK
RST
. .
. .
. .
Figure 7-19: Instantiate IDELAYCTRL Without LOC Constraints - RDY Connected
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Input/Output Delay Element (IODELAY)
Instantiated by user
REFCLK RDY
IDELAYCTRL
RST
REFCLK RDY
IDELAYCTRL
RST
.
Replicated for
all IDELAYCTRL .
sites
.
REFCLK RDY
IDELAYCTRL
RST
Instantiated by user
REFCLK RDY
IDELAYCTRL
RST
REFCLK RDY
IDELAYCTRL
RST
.
Replicated for
.
all IDELAYCTRL
sites
.
REFCLK RDY
IDELAYCTRL
RST
RDY signal ignored
Auto-generated by
mapper tool
ug190_7_13_041206
RDY
Auto-generated by
mapper tool
ug190_7_14_041306
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