Xilinx Virtex-5 FPGA User Manual page 91

Input muxes select the reference and feedback clocks from either the IBUFG, BUFG, IBUF,
PLL outputs, or one of the DCMs. Each clock input has a programmable counter D. The
Phase-Frequency Detector (PFD) compares both phase and frequency of the input
(reference) clock and the feedback clock. Only the rising edges are considered because as
long as a minimum High/Low pulse is maintained, the duty cycle is not important. The
PFD is used to generate a signal proportional to the phase and frequency between the two
clocks. This signal drives the Charge Pump (CP) and Loop Filter (LF) to generate a
reference voltage to the VCO. The PFD produces an up or down signal to the charge pump
and loop filter to determine whether the VCO should operate at a higher or lower
frequency. When VCO operates at too high of a frequency, the PFD activates a down signal,
causing the control voltage to be reduced decreasing the VCO operating frequency. When
the VCO operates at too low of a frequency, an up signal will increase voltage. The VCO
produces eight output phases. Each output phase can be selected as the reference clock to
the output counters
given customer design. A special counter, M, is also provided. This counter controls the
feedback clock of the PLL allowing a wide range of frequency synthesis.
X-Ref Target - Figure 3-3
General
Routing
CLKIN1
CLKIN2
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
(Figure
Clock
Switch
Circuit
D
CLKFB
Figure 3-3: Detailed PLL Block Diagram
www.xilinx.com
3-3.) Each counter can be independently programmed for a
Lock Detect
Lock Monitor
PFD CP LF
CLKFBOUT
M
VCO feedback phase
selection for negative
phase-shift affecting
all outputs
Introduction
Lock
8-phase
taps
O0
VCO
O1
O2
8
O3
O4
O5
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