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Xilinx VC707 Manual
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Xilinx VC707 Manual

Mig design creation
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VC707 MIG Design Creation
July 2012
XTP143

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Summary of Contents for Xilinx VC707

  • Page 1 VC707 MIG Design Creation July 2012 XTP143...

  • Page 2: Revision History

    NOTICE OF DISCLAIMER: The information disclosed to you hereunder (the “Information”) is provided “AS-IS” with no warranty of any kind, express or implied. Xilinx does not assume any liability arising from your use of the Information. You are responsible for obtaining any rights you may require for your use of this Information.
  • Page 3 Overview VC707 Board VC707 Setup Generate MIG Example Design Modifications to Example Design Compile Example Design Run MIG Example Design References Note: This presentation applies to the VC707...
  • Page 4 Xilinx VC707 Board Note: Presentation applies to the VC707...
  • Page 5 ISE Software Requirement Xilinx ISE 14.2 software – Apply AR50886 Note: Presentation applies to the VC707...
  • Page 6 ChipScope Pro Software Requirement Xilinx ChipScope Pro 14.2 software Note: Presentation applies to the VC707...
  • Page 7 Generate MIG Example Design Open the CORE Generator Start → All Programs → Xilinx Design Tools → ISE Design Suite 14.2 → ISE Design Tools → 32-bit Tools → CORE Generator Create a new project; select File → New Project...
  • Page 8 Create a project in a new directory named: – vc707_mig_design Select Part Set the Part (as shipped on the VC707): – Family: Virtex7 – Device: xc7vx485t – Package: ffg1761 – Speed Grade: -2 Select Generation Note: Presentation applies to the VC707...
  • Page 9 Generate MIG Example Design Under Generation – Set the Design Entry to Verilog Click OK Note: Presentation applies to the VC707...
  • Page 10 Generate MIG Example Design Right click on MIG 7 Series Version 1.5 – Select Customize and Generate Note: Presentation applies to the VC707...
  • Page 11 Generate MIG Example Design Leave this page as is – Click Next...
  • Page 12 Generate MIG Example Design Leave this page as is – Click Next...
  • Page 13 Generate MIG Example Design Leave this page as is – Click Next...
  • Page 14 Generate MIG Example Design Select Memory Type – DDR3 SDRAM – Click Next...
  • Page 15 Generate MIG Example Design Select – Clock Period: 1250 ps – Type: SODIMMs – Part: MT8JTF12864HZ-1G6...
  • Page 16 Generate MIG Example Design Scroll down on this page and select: – Data Mask: Checked – Ordering: Normal – Click Next...
  • Page 17 Generate MIG Example Design Select: – Input Clock Period: 5000 ps – RTT: RZQ/6 – Click Next...
  • Page 18 Generate MIG Example Design Select – Debug: ON – Click Next...
  • Page 19 Generate MIG Example Design Select – DCI Cascade: Checked – Click Next...
  • Page 20 Generate MIG Example Design Select Fixed Pin Out – Click Next...
  • Page 21 Open the VC707 MIG Design Files (14.2 CES) – Available through http://www.xilinx.com/vc707 – Extract the file, “example_top.ucf” only to C:\vc707_mig_design – Contains the UCF constraints needed for VC707 MIG design – This zip file will be needed later in the presentation Note: Presentation applies to the VC707...
  • Page 22 Generate MIG Example Design Select ReadUCF – Open the file: example_top.ucf...
  • Page 23 Generate MIG Example Design Once it finishes reading in the UCF, click Validate – Click OK...
  • Page 24 Generate MIG Example Design The Next button is enabled once the pinout is validated. – Click Next...
  • Page 25 Generate MIG Example Design Make the following settings: – Set sys_clk_p/n to – Bank 38 – Pin Number: G19/F19(CC_P/N) – Set clk_ref_p/n to – Bank 38 – Pin Number: E19/E18(CC_P/N) – Click Next...
  • Page 26 Generate MIG Example Design Make the following settings: – Set sys_rst to – Bank 15 – Pin Number: AV40(MRCC_P) – Click Next...
  • Page 27 Generate MIG Example Design Leave this page as is – Click Next...
  • Page 28 Generate MIG Example Design Accept Simulation license, if desired – Otherwise, Decline license – Click Next...
  • Page 29 Generate MIG Example Design Leave this page as is – Click Next...
  • Page 30 Generate MIG Example Design Click Generate...
  • Page 31 Generate MIG Example Design After the MIG core finishes generating, click Close on the Datasheet window Note: Presentation applies to the VC707...
  • Page 32 Generate MIG Example Design MIG design appears in Project IP Note: Presentation applies to the VC707...
  • Page 33 Modifications to Example Design Unzip the VC707 MIG Design Files (14.2 CES) to your C:\vc707_mig_design directory – Contains several changes needed to support Virtex-7 devices with MIG Note: Overwrites some of the CORE Generator output files...
  • Page 34 – Added CONFIG DCI_CASCADE = “38 37 39”; to UCF; for more information on using the DCI_CASCADE constraint for 7 Series refer to AR44746 – Changed RST_ACT_LOW to “0”; refer to UG586 for more details on using the RST_ACT_LOW parameter Note: Presentation applies to the VC707...
  • Page 35 Compile Example Design Start a ISE Design Suite Command Prompt and enter these commands: cd C:\vc707_mig_design\mig_7series_v1_6\example_design\par ise_flow.bat Note: Presentation applies to the VC707...
  • Page 36 VC707 Setup Connect a USB Type-A to Micro-B cable to the USB JTAG (Digilent) connector on the VC707 board – Connect this cable to your PC – Power on the VC707 board...
  • Page 37 Run MIG Example Design Open ChipScope Pro and select JTAG Chain -> Digilent USB Cable… Verify 30 MHz operation and click OK (2) Note: Presentation applies to the VC707...
  • Page 38 Run MIG Example Design Click OK (1) Note: Presentation applies to the VC707...
  • Page 39 Run MIG Example Design Select Device → DEV:0 MyDevice0 (XC7VX485T) → Configure… Select <Design Path>\mig_7series_v1_6\example_design\par\example_top.bit Note: Presentation applies to the VC707...
  • Page 40 Run MIG Example Design After bitstream loads, LED 0 (right most LED) will be lit, and LED1 will be blinking LED 3 will light and stay on – This indicates Calibration has completed If an error occurs, LED 0 will go out and LED 2 will light –...
  • Page 41 Run MIG Example Design Select File → Open Project… Select <Design Path>\ready_for_download\vc707_mig.cpj Note: Presentation applies to the VC707...
  • Page 42 Run MIG Example Design Click on Trigger Setup to view trigger settings Note: Presentation applies to the VC707...
  • Page 43 Run MIG Example Design Click on Waveform; click the Trigger Immediate button (1) Note: Presentation applies to the VC707...
  • Page 44 Run MIG Example Design View waveforms Data is valid when dbg_rddata_valid is high Note: Presentation applies to the VC707...
  • Page 45 Run MIG Example Design Zoom in to view data Note: Presentation applies to the VC707...
  • Page 46 Adjust Data Pattern using VIO Console Select VIO Console 3 Set vio_modify_enable to 1 Note: Presentation applies to the VC707...
  • Page 47 Adjust Data Pattern using VIO Console Set vio_data_mode_value to “7” for PRBS_DATA Note: Presentation applies to the VC707...
  • Page 48 Run MIG Example Design Press and release the CPU RESET switch, SW8, after each change to vio_modify_enable or vio_data_mode_value...
  • Page 49 Run MIG Example Design Click on Waveform; click the Trigger Immediate button (1) View PRBS data Note: Presentation applies to the VC707...
  • Page 50 References...
  • Page 51 References Virtex-7 Memory – 7 Series FPGAs Memory Interface Solutions User Guide – UG586 • http://www.xilinx.com/support/documentation/ip_documentation/ mig_7series/v1_4/ug586_7Series_MIS.pdf ChipScope Pro – ChipScope Pro Software and Cores User Guide • http://www.xilinx.com/support/documentation/sw_manuals/ xilinx14_1/chipscope_pro_sw_cores_ug029.pdf...
  • Page 52 Documentation...
  • Page 53 Documentation Virtex-7 – Virtex-7 FPGA Family • http://www.xilinx.com/products/silicon-devices/fpga/virtex-7/index.htm VC707 Documentation – Virtex-7 FPGA VC707 Evaluation Kit • http://www.xilinx.com/products/boards-and-kits/EK-V7-VC707-G.htm – VC707 User Guide • http://www.xilinx.com/support/documentation/boards_and_kits/ ug885_VC707_Eval_Bd.pdf...