Transceiver Debug - Xilinx LogiCORE IP AXI Product Manual

Identifying Errors
See Abnormal Conditions in Chapter 3
side of the AXI Bridge for PCI Express handle abnormal conditions.
Next Steps
If the debug suggestions listed previously do not resolve the issue, open a support case or
visit the Xilinx User Community forums to have the appropriate Xilinx expert assist with the
issue.
To create a technical support case in WebCase, see the Xilinx website at:
www.xilinx.com/support/clearexpress/websupport.htm
Items to include when opening a case:
Detailed description of the issue and results of the steps listed above.
°
Vivado lab tools captures taken in the steps above.
°
To discuss possible solutions, use the Xilinx User Community:
forums.xilinx.com/xlnx/

Transceiver Debug

Table B-1 describes the ports used to debug transceiver related issues.
RECOMMENDED:
Table B-1: Ports Used for Transceiver Debug
Port
pipe_txprbssel
pipe_rxprbssel
pipe_rxprbsforceerr
pipe_rxprbscntrreset
pipe_loopback
pipe_rxprbserr
pipe_rst_fsm
pipe_qrst_fsm
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Debugging transceiver issues is recommended for advanced users only.
Direction Width
3
I
I 3
I 1
1
I
I 1
O 1
O
O
www.xilinx.com
for information about how the Slave side and Master
Description
PRBS input.
PRBS input.
PRBS input.
PRBS input.
PIPE loopback.
PRBS output.
Should be examined if pipe_rst_idle is stuck at 0.
Should be examined if pipe_rst_idle is stuck at 0.
Appendix B: Debugging
102
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