Xilinx Virtex-5 FPGA User Manual page 188
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- User manual (140 pages) ,
- User manual (108 pages) ,
- User manual (28 pages)
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Chapter 5: Configurable Logic Blocks (CLBs)
X-Ref Target - Figure 5-13
188
A6 (CX)
DX
D
A[6:0]
(CLK)
WCLK
WE
DPRA[6:0]
AX
Figure 5-13: Distributed RAM (RAM128X1D)
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RAM128X1D
DPRAM64
O6
DI1
6
A[6:1]
7
WA[7:1]
CLK
(WE)
WE
DPRAM64
O6
DI1
6
A[6:1]
7
WA[7:1]
CLK
WE
DPRAM64
O6
DI1
6
A[6:1]
7
WA[7:1]
CLK
WE
DPRAM64
O6
DI1
6
A[6:1]
7
WA[7:1]
CLK
WE
SPO
D Q
F7BMUX
(Optional)
DPO
D Q
F7AMUX
(Optional)
UG190_5_13_050506
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
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