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Xilinx VCU1287 User Manual

Xilinx VCU1287 User Manual

Characterization board
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VCU1287
Characterization Board
User Guide
UG1121 (v1.0) December 11, 2015

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Summary of Contents for Xilinx VCU1287

  • Page 1 VCU1287 Characterization Board User Guide UG1121 (v1.0) December 11, 2015...

  • Page 2: Revision History

    Revision History The following table shows the revision history for this document. Date Version Revision 12/11/2015 Initial Xilinx release. VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...

  • Page 3: Table Of Contents

    VCU1287 Board XDC Listing........
  • Page 4 Xilinx Resources ........

  • Page 5: Chapter 1: Introduction

    Chapter 1 Introduction Overview This user guide describes the components, features, and operation of the VCU1287 UltraScale® FPGA GTH and GTY transceivers characterization board. The VCU1287 board provides the hardware environment for characterizing and evaluating the GTH and GTY transceivers available on the UltraScale XCVU095-FFVB2104E FPGA. The VCU1287 board...

  • Page 6: Block Diagram

    Chapter 1: Introduction Block Diagram The VCU1287 board block diagram is shown in Figure 1-1. X-Ref Target - Figure 1-1 MGT Transceivers FMC1 Interface QUAD 124 Power In High Performance QUAD 125 12VDC QUAD 126 QUAD 127 QUAD 128 FMC2 Interface...

  • Page 7: Board Features

    Chapter 1: Introduction Board Features The VCU1287 characterization board features are listed here. Detailed information for each feature is provided in Chapter 3, Board Component Descriptions. • UltraScale XCVU095-FFVB2104E FPGA • BullsEye cable access to all 32 GTH and 32 GTY transceivers on the UltraScale XCVU095-FFVB2104E FPGA •...

  • Page 8: Chapter 2: Board Setup And Configuration

    IMPORTANT: board. The VCU1287 board can be damaged by electrostatic discharge (ESD). Follow standard ESD CAUTION! prevention measures when handling the board. Do not remove the rubber feet from the board. The feet provide clearance to prevent short CAUTION! circuits on the back side of the board.
  • Page 9 Chapter 2: Board Setup and Configuration X-Ref Target - Figure 2-1 Figure 2-1: VCU1287 Characterization Board Components VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 10 Chapter 2: Board Setup and Configuration Table 2-1: VCU1287 Board Components Callout Reference Designator Feature Description Virtex UltraScale XCVU095-FFVB2104E Device Power Switch 12V mini-fit connector (12V Input Power) GTY transceiver connector pads Q124, Q125, Q126, Q127, Q128, J37, J155, J38, J80, J39,...
  • Page 11 Chapter 2: Board Setup and Configuration Table 2-1: VCU1287 Board Components (Cont’d) Callout Reference Designator Feature Description Bank 224-233 GTH transceiver power supply module (A list of jumpers and switches and their required positions for normal J46, J124 board operation is provided in Appendix A, Default Jumper Settings.)

  • Page 12: Chapter 3: Board Component Descriptions

    Figure 2-1) using the 12V AC adapter that is provided with the VCU1287 board characterization kit. J28 is a 6-pin (2 x 3), right angle, mini-fit connector. When supplying 12V through J28, use only the power supply provided for use with this CAUTION! board (Xilinx part number 3800033).
  • Page 13 75W because of Q1 limitation. Power Switch The VCU1287 board main power is turned On or Off using switch SW1 (callout 2, Figure 2-1). When the switch is in the ON position, power is applied to the board and the...
  • Page 14 1.8V at 2.5A max GTH Power Module Quads 224-233 MGTAVCC_R 1.0V at 12.0A max MGTAVTT_R 1.2V at 20A max MGTVCCAUX_R 1.8V at 2.5A max Figure 3-1: VCU1287 Board Power Supply Block Diagram VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 15 Chapter 3: Board Component Descriptions The VCU1287 board uses power regulators and PMBus compliant digital PWM system controllers from Maxim Integrated to supply the FPGA logic and utilities voltages listed in Table 3-1. The board can also be configured to use an external bench power supply for each voltage.
  • Page 16 Table 3-2: FPGA Logic and MGT Transceiver Rails Power Rail Net External Supply Power Regulation Name Connector (s) Jumper VCCINT VCCAUX VCCBRAM FPGA Logic VCCO_HP VCCO_HR MGTAVCC_R MGTAVTT_R GTH Transceiver MGTVCCAUX_R VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 17 Voltage and current monitoring and control for Maxim power system is available through either the VCU1287 board system controller or the MaximPower Tool software GUI. The VCU1287 board system controller is the most convenient way to monitor the voltage and current values for the power rails listed in Table 3-2.
  • Page 18 FPGA power rails and the transceiver power rails using the Maxim InTune digital power GUI. X-Ref Target - Figure 3-3 Figure 3-3: MGT PMBus isolation More information about the power system components used by the VCU1287 board is available from the Maxim Integrated InTune digital power website [Ref VCU1287 Characterization Board www.xilinx.com...
  • Page 19 MGTAVTT_R, and MGTVCCAUX_R power rails, which connect to the FPGA GTH transceivers. Two MGT power modules from Maxim Integrated are provided with the VCU1287 board for evaluation. The modules can be plugged into connectors J138 and J93 or J46 and J124 in...
  • Page 20 The MGT Power Module MUST be removed when providing external power to the MGT CAUTION! transceiver rails. Information about the available MGT power modules included with the VCU1287 board characterization kit is available from the vendor websites [Ref Active Heat Sink Power Connector...
  • Page 21 J99.2 - 12V Blue J99.3 - NC Figure 3-6 shows the heat sink fan power connector J99. X-Ref Target - Figure 3-6 Figure 3-6: Heat Sink Fan Power Connector J99 VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 22 Platform cable USB JTAG cable connector (callout 7, Figure 2-1). A JTAG connector (J2) can be used to provide access to the JTAG chain using the Xilinx Platform Cable USB, Platform Cable USB II, or Parallel Cable IV (PCIV) configuration cable.
  • Page 23 During FPGA initialization, the INIT LED illuminates RED. When FPGA initialization has completed, the LED illuminates GREEN. System Controller The VCU1287 board utilizes a Xilinx XC7Z010-CLG225 Zynq-7000 AP SoC U38 (callout 35, Figure 2-1) system controller that can be used to: •...
  • Page 24 System Controller GPIO Pushbuttons SW5, SW6, SW10, SW11, SW12 (callout 38, Figure 2-1) are active-high pushbuttons connected to GPIO pins on the system controller. See GPIO Data Menu for more details. VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 25 Callout 24, Figure 2-1 VCU1287 uses a single chip USB-to-dual UART bridge (U32, Silicon Laboratories CP2105) for simultaneous serial communication between a host terminal and the UltraScale FPGA, and between a host terminal and the system controller. The onboard micro-B receptacle USB...
  • Page 26 GPIO IN/OUT AR16 SelectIO IN/OUT LVCMOS18 UART_GPIO_3 GPIO IN/OUT The second port of the CP2105 USB-to-dual UART is connected to the onboard system controller. See Appendix D, System Controller. VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 27 Output oscillator Differential SMA MRCC Pin Inputs The VCU1287 board provides two pairs of differential SMA transceiver clock inputs (callout Figure 2-1) that can be used for connecting to an external clock source. The FPGA MRCC pins are connected to the SMA connectors as shown in Table 3-9.
  • Page 28 2-1) connects to the clock module interface connector (J36) and provides a programmable, low-noise and low-jitter clock source for the VCU1287 board. The clock module maps to FPGA I/O by way of 14 control pins, 2 LVDS pairs, 1 regional clock pair, and 1 reset pin.
  • Page 29 User switch Input LVCMOS18 USER_SW4 AR13 User switch Input LVCMOS18 USER_SW5 AV16 User switch Input LVCMOS18 USER_SW6 AW16 User switch Input LVCMOS18 USER_SW7 AW15 User switch Input LVCMOS18 USER_SW8 VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 30 3-13. These switches can be used for any purpose. Table 3-13: User Pushbuttons FPGA(U1) Schematic Reference Net Name Designator Function Direction IOSTANDARD AN14 User push button Input LVCMOS18 USER_PB1 AM14 User push button Input LVCMOS18 USER_PB2 VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 31 Chapter 3: Board Component Descriptions MGT Transceivers and Reference Clocks The VCU1287 board provides access to all GTY and GTH transceiver and reference clock pins on the XCVU095 FPGA as shown in Figure 3-11. The MGT transceivers are grouped into...
  • Page 32 124_RX2_P 2494.19 AV44 124_RX3_N 3018.544 AV43 124_RX3_P 3019.123 BF43 124_TX0_N 2556.328 BF42 124_TX0_P 2556.96 BD43 124_TX1_N 2363.323 BD42 124_TX1_P 2362.718 BB43 124_TX2_N 3014.59 BB42 124_TX2_P 3015.086 AW41 124_TX3_N 2748.806 VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 33 126_TX0_N 4402.107 AN40 126_TX0_P 4403.051 AM39 126_TX1_N 4652.186 AM38 126_TX1_P 4652.806 AL41 126_TX2_N 3654.072 AL40 126_TX2_P 3653.646 AK39 126_TX3_N 3798.355 AK38 126_TX3_P 3797.947 AJ46 127_RX0_N 3978.188 AJ45 127_RX0_P 3977.562 VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 34 128_TX1_N 3551.521 AD38 128_TX1_P 3551.324 AC41 128_TX2_N 2497.894 AC40 128_TX2_P 2497.382 AB39 128_TX3_N 2753.954 AB38 128_TX3_P 2753.46 AA46 129_RX0_N 3187.684 AA45 129_RX0_P 3188.041 129_RX1_N 2165.289 129_RX1_P 2166.051 129_RX2_N 2023.319 VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 35 J141 2786.723 130_TX3_P J141 2788.314 131_RX0_N J142 3483.317 131_RX0_P J142 3450.975 131_RX1_N J142 3131.583 131_RX1_P J142 3127.369 131_RX2_N J142 2636.221 131_RX2_P J142 2632.322 131_RX3_N J142 4093.547 131_RX3_P J142 4093.919 VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 36 2428.943 224_TX0_P 2433.409 224_TX1_N 2468.88 224_TX1_P 2464.789 224_TX2_N 2500.467 224_TX2_P 2503.893 224_TX3_N 3016.944 224_TX3_P 3017.689 225_RX0_N 3181.169 225_RX0_P 3177.517 225_RX1_N 2570.369 225_RX1_P 2567.203 225_RX2_N 3343.092 225_RX2_P 3341.453 225_RX3_N 3319.371 VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 37 3302.81 226_TX2_N 3364.517 226_TX2_P 3362.592 226_TX3_N 3317.108 226_TX3_P 3312.975 227_RX0_N 3227.755 227_RX0_P 3223.526 227_RX1_N 2709.811 227_RX1_P 2710.042 227_RX2_N 2362.249 227_RX2_P 2365.911 227_RX3_N 3215.269 227_RX3_P 3210.717 227_TX0_N 3241.15 227_TX0_P 3236.92 VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 38 2650.866 228_TX3_P 2646.679 229_RX0_N 2529.004 229_RX0_P 2524.797 229_RX1_N 2091.731 229_RX1_P 2095.424 229_RX2_N 2137.807 229_RX2_P 2141.003 229_RX3_N 2511.348 229_RX3_P 2508.271 229_TX0_N 2571.308 229_TX0_P 2567.078 229_TX1_N 2368.077 229_TX1_P 2363.848 229_TX2_N 2502.29 VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 39 J156 3460.674 231_RX3_P J156 3456.005 231_TX0_N J156 3456.058 231_TX0_P J156 3451.829 231_TX1_N J156 3099.879 231_TX1_P J156 3095.669 231_TX2_N J156 3466.734 231_TX2_P J156 3462.857 231_TX3_N J156 3619.237 231_TX3_P J156 3619.035 VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 40 128_REFCLK0_P AE37 128_REFCLK1_N AE36 128_REFCLK1_P AC37 129_REFCLK0_N AC36 129_REFCLK0_P AA37 129_REFCLK1_N AA36 129_REFCLK1_P 130_REFCLK0_N J141 130_REFCLK0_P J141 130_REFCLK1_N J141 130_REFCLK1_P J141 131_REFCLK0_N J142 131_REFCLK0_P J142 131_REFCLK1_N J142 131_REFCLK1_P J142 VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 41 227_REFCLK0_P AF10 227_REFCLK1_N AF11 227_REFCLK1_P AD10 228_REFCLK0_N AD11 228_REFCLK0_P AB10 228_REFCLK1_N AB11 228_REFCLK1_P 229_REFCLK0_P 229_REFCLK0_N 229_REFCLK1_N 229_REFCLK1_P 230_REFCLK0_N 230_REFCLK0_P 230_REFCLK1_N 230_REFCLK1_P 231_REFCLK0_N J156 231_REFCLK0_P J156 231_REFCLK1_N J156 231_REFCLK1_P J156 VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 42 Callout 30, 31, and 32, Figure 2-1 The VCU1287 board features two high pin count (HPC) connectors as defined by the VITA 57.1 FPGA Mezzanine card (FMC) specification. The FMC HPC connector is a 10 x 40 position socket. See Appendix B, VITA 57.1 FMC Connector Pinouts...
  • Page 43 Chapter 3: Board Component Descriptions The FMC HPC connectors on the VCU1287 board are identified as FMC1 at JA2, FMC2 at JA3, and FMC3 at JA4. The connections for each of these connectors are listed in Table 3-18, Table 3-19 Table 3-20, respectively.
  • Page 44 FMC1_HA15P FMC1_HA15N FMC1_HA16P FMC1_HA16N FMC1_HA17_CC_P FMC1_HA17_CC_N FMC1_HA18P FMC1_HA18N FMC1_HA19P FMC1_HA19N FMC1_HA20P FMC1_HA20N FMC1_HA21P FMC1_HA21N FMC1_HA22P FMC1_HA22N FMC1_HA23P FMC1_HA23N FMC1_HB00_CC_P FMC1_HB00_CC_N FMC1_HB01_CC_P FMC1_HB01_CC_N FMC1_HB02P FMC1_HB02N FMC1_HB03P FMC1_HB03N FMC1_HB04P FMC1_HB04N FMC1_HB05P VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 45 FMC1_HB10N FMC1_HB11P FMC1_HB11N FMC1_HB12P FMC1_HB12N FMC1_HB13P FMC1_HB13N FMC1_HB14P FMC1_HB14N FMC1_HB15P FMC1_HB15N FMC1_HB16P FMC1_HB16N AD33 FMC1_LA00_CC_P AE33 FMC1_LA00_CC_N AE31 FMC1_LA01_CC_P AE32 FMC1_LA01_CC_N FMC1_LA02P FMC1_LA02N FMC1_LA03P FMC1_LA03N FMC1_LA04P FMC1_LA04N FMC1_LA05P FMC1_LA05N VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 46 AF34 FMC1_LA13P AG34 FMC1_LA13N AH33 FMC1_LA14P AJ33 FMC1_LA14N AH34 FMC1_LA15P AJ34 FMC1_LA15N AJ31 FMC1_LA16P AK31 FMC1_LA16N FMC1_LA17_CC_P FMC1_LA17_CC_N FMC1_LA18_CC_P FMC1_LA18_CC_N FMC1_LA19P FMC1_LA19N FMC1_LA20P FMC1_LA20N FMC1_LA21P FMC1_LA21N FMC1_LA22P FMC1_LA22N FMC1_LA23P VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 47 Table 3-19: VITA 57.1 FMC2 HPC Connections at JA3 U1 FPGA Pin Net Name FMC Pin AV26 FMC2_CLK0_M2C_P AW26 FMC2_CLK0_M2C_N AW28 FMC2_CLK1_M2C_P AY28 FMC2_CLK1_M2C_N AY26 FMC2_LA00_CC_P AY27 FMC2_LA00_CC_N AW25 FMC2_LA01_CC_P AY25 FMC2_LA01_CC_N AL27 FMC2_LA02P AL28 FMC2_LA02N VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 48 FMC2_LA13P BB25 FMC2_LA13N BC26 FMC2_LA14P BC27 FMC2_LA14N BE25 FMC2_LA15P BF25 FMC2_LA15N BD26 FMC2_LA16P BE26 FMC2_LA16N BD28 FMC2_LA17_CC_P BE28 FMC2_LA17_CC_N BE27 FMC2_LA18_CC_P BF27 FMC2_LA18_CC_N BF28 FMC2_LA19P BF29 FMC2_LA19N AR26 FMC2_PRSNT_M2C_L VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 49 FMC3_CLK3_BIDIR_P FMC3_CLK3_BIDIR_N FMC3_HA00_CC_P FMC3_HA00_CC_N FMC3_HA01_CC_P FMC3_HA01_CC_N FMC3_HA02P FMC3_HA02N FMC3_HA03P FMC3_HA03N FMC3_HA04P FMC3_HA04N FMC3_HA05P FMC3_HA05N FMC3_HA06P FMC3_HA06N FMC3_HA07P FMC3_HA07N FMC3_HA08P FMC3_HA08N FMC3_HA09P FMC3_HA09N FMC3_HA10P FMC3_HA10N FMC3_HA11P FMC3_HA11N FMC3_HA12P FMC3_HA12N FMC3_HA13P VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 50 FMC3_HA23N AY35 FMC3_HB00_CC_P AY36 FMC3_HB00_CC_N BA34 FMC3_HB01_CC_P BB34 FMC3_HB01_CC_N AL34 FMC3_HB02P AM34 FMC3_HB02N AL32 FMC3_HB03P AM32 FMC3_HB03N AN32 FMC3_HB04P AN33 FMC3_HB04N AN34 FMC3_HB05P AP34 FMC3_HB05N AP33 FMC3_HB06P AR33 FMC3_HB06N VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 51 BC34 FMC3_HB16P BD34 FMC3_HB16N BA35 FMC3_HB17_CC_P BB35 FMC3_HB17_CC_N BB38 FMC3_HB18P BC38 FMC3_HB18N BC39 FMC3_HB19P BD39 FMC3_HB19N BD40 FMC3_HB20P BE40 FMC3_HB20N BE37 FMC3_HB21P BF37 FMC3_HB21N FMC3_LA00_CC_P FMC3_LA00_CC_N FMC3_LA01_CC_P FMC3_LA01_CC_N FMC3_LA02P VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 52 FMC3_LA05N FMC3_LA06P FMC3_LA06N FMC3_LA07P FMC3_LA07N FMC3_LA08P FMC3_LA08N FMC3_LA09P FMC3_LA09N FMC3_LA10P FMC3_LA10N FMC3_LA11P FMC3_LA11N FMC3_LA12P FMC3_LA12N FMC3_LA13P FMC3_LA13N FMC3_LA14P FMC3_LA14N FMC3_LA15P FMC3_LA15N FMC3_LA16P FMC3_LA16N FMC3_LA17_CC_P FMC3_LA17_CC_N FMC3_LA18_CC_P FMC3_LA18_CC_N FMC3_LA19P FMC3_LA19N VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 53 FMC3_LA20P FMC3_LA20N FMC3_LA21P FMC3_LA21N FMC3_LA22P FMC3_LA22N FMC3_LA23P FMC3_LA23N FMC3_LA24P FMC3_LA24N FMC3_LA25P FMC3_LA25N FMC3_LA26P FMC3_LA26N FMC3_LA27P FMC3_LA27N FMC3_LA28P FMC3_LA28N FMC3_LA29P FMC3_LA29N FMC3_LA30P FMC3_LA30N FMC3_LA31P FMC3_LA31N FMC3_LA32P FMC3_LA32N FMC3_LA33P FMC3_LA33N FMC3_PRSNT_M2C_L VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 54 I2C/PMBus communication between the bus master (system controller or FPGA) and six sub-systems: • Onboard regulators and power monitoring • SuperClock-2 module • System controller EEPROM • FMC1 connector • FMC2 connector • FMC3 connector VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 55 3-14). J121 and J125 are used to enable or disable the bus repeaters and isolate the system controller or the UltraScale FPGA I2C bus. X-Ref Target - Figure 3-14 Figure 3-14: I2C Bus Multiplexer and Upstream Repeater VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...

  • Page 56: Appendix A: Default Jumper Settings

    Appendix A Default Jumper Settings Introduction Table A-1 lists the jumpers that must be installed on the VCU1287 board for proper operation. These jumpers must be installed except where specifically noted in this user guide. Any jumper not listed in Table A-1 should be left open for normal operation.
  • Page 57 Appendix Appendix A: Default Jumper Settings Table A-1: Default Jumper Settings (Cont’d) Reference Jumper/Dip-switch Name Board Location Comments Designator Position SW13.4 ADDR2 Upper Right SW13.5 ADDR3 Upper Right VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...

  • Page 58: Appendix B: Vita 57.1 Fmc Connector Pinouts

    Figure B-1 provides a cross-reference of signal names to pin coordinates for the VITA 57.1 FMC HPC connector. X-Ref Target - Figure B-1 Figure B-1: FMC HPC Connector Pinout VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...

  • Page 59: Appendix C: Master Constraints File Listing

    VCU1287 UltraScale FPGA GTH and GTY Transceiver Characterization Board. Net names in the listed constraints correlate with net names on the VCU1287 board schematic. Identify the appropriate pins and replace the net names with net names in the user RTL.
  • Page 60 PACKAGE_PIN AH33 [get_ports "FMC1_LA14P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_LA14P"] set_property PACKAGE_PIN AJ33 [get_ports "FMC1_LA14N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_LA14N"] set_property PACKAGE_PIN AH34 [get_ports "FMC1_LA15P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_LA15P"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 61 IOSTANDARD LVCMOS18 [get_ports "FMC1_LA30N"] set_property PACKAGE_PIN R30 [get_ports "FMC1_LA31P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_LA31P"] set_property PACKAGE_PIN P30 [get_ports "FMC1_LA31N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_LA31N"] set_property PACKAGE_PIN U30 [get_ports "FMC1_LA32P"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 62 PACKAGE_PIN A37 [get_ports "FMC1_HA11P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_HA11P"] set_property PACKAGE_PIN A38 [get_ports "FMC1_HA11N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_HA11N"] set_property PACKAGE_PIN B39 [get_ports "FMC1_HA12P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_HA12P"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 63 IOSTANDARD LVCMOS18 [get_ports "FMC1_HB01_CC_P"] set_property PACKAGE_PIN J29 [get_ports "FMC1_HB01_CC_N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_HB01_CC_N"] set_property PACKAGE_PIN E28 [get_ports "FMC1_HB02P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_HB02P"] set_property PACKAGE_PIN D28 [get_ports "FMC1_HB02N"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 64 PACKAGE_PIN R27 [get_ports "FMC1_HB15N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_HB15N"] set_property PACKAGE_PIN T28 [get_ports "FMC1_HB16P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_HB16P"] set_property PACKAGE_PIN R28 [get_ports "FMC1_HB16N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC1_HB16N"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 65 PACKAGE_PIN AV27 [get_ports "FMC2_LA10P"] set_property IOSTANDARD LVCMOSxx [get_ports "FMC2_LA10P"] set_property PACKAGE_PIN AV28 [get_ports "FMC2_LA10N"] set_property IOSTANDARD LVCMOSxx [get_ports "FMC2_LA10N"] set_property PACKAGE_PIN BA27 [get_ports "FMC2_LA11P"] set_property IOSTANDARD LVCMOSxx [get_ports "FMC2_LA11P"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 66 LVCMOS18 [get_ports "FMC3_CLK3_BIDIR_P"] set_property PACKAGE_PIN H23 [get_ports "FMC3_CLK3_BIDIR_N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_CLK3_BIDIR_N"] #FMC3 LA set_property PACKAGE_PIN G15 [get_ports "FMC3_LA00_CC_P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_LA00_CC_P"] set_property PACKAGE_PIN F15 [get_ports "FMC3_LA00_CC_N"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 67 PACKAGE_PIN K16 [get_ports "FMC3_LA14P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_LA14P"] set_property PACKAGE_PIN K15 [get_ports "FMC3_LA14N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_LA14N"] set_property PACKAGE_PIN N16 [get_ports "FMC3_LA15P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_LA15P"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 68 IOSTANDARD LVCMOS18 [get_ports "FMC3_LA28N"] set_property PACKAGE_PIN K25 [get_ports "FMC3_LA29P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_LA29P"] set_property PACKAGE_PIN J25 [get_ports "FMC3_LA29N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_LA29N"] set_property PACKAGE_PIN L23 [get_ports "FMC3_LA30P"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 69 PACKAGE_PIN E21 [get_ports "FMC3_HA09P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_HA09P"] set_property PACKAGE_PIN E20 [get_ports "FMC3_HA09N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_HA09N"] set_property PACKAGE_PIN E18 [get_ports "FMC3_HA10P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_HA10P"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 70 LVCMOS18 [get_ports "FMC3_HA23P"] set_property PACKAGE_PIN M17 [get_ports "FMC3_HA23N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_HA23N"] #FMC3 HB set_property PACKAGE_PIN AY35 [get_ports "FMC3_HB00_CC_P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_HB00_CC_P"] set_property PACKAGE_PIN AY36 [get_ports "FMC3_HB00_CC_N"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 71 PACKAGE_PIN BD36 [get_ports "FMC3_HB14P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_HB14P"] set_property PACKAGE_PIN BE36 [get_ports "FMC3_HB14N"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_HB14N"] set_property PACKAGE_PIN BD35 [get_ports "FMC3_HB15P"] set_property IOSTANDARD LVCMOS18 [get_ports "FMC3_HB15P"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 72 IOSTANDARD LVCMOS18 [get_ports "CM_H_INT_ALRM"] set_property PACKAGE_PIN L13 [get_ports "CM_LVDS1_P"] set_property IOSTANDARD LVCMOS18 [get_ports "CM_LVDS1_P"] set_property PACKAGE_PIN K13 [get_ports "CM_LVDS1_N"] set_property IOSTANDARD LVCMOS18 [get_ports "CM_LVDS1_N"] set_property PACKAGE_PIN J33 [get_ports "CM_LVDS2_P"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 73 PACKAGE_PIN K32 [get_ports "CLK_DIFF_1_N"] set_property IOSTANDARD LVDS [get_ports "CLK_DIFF_1_N"] set_property PACKAGE_PIN M31 [get_ports "CLK_DIFF_2_P"] set_property IOSTANDARD LVDS [get_ports "CLK_DIFF_2_P"] set_property PACKAGE_PIN M32 [get_ports "CLK_DIFF_2_N"] set_property IOSTANDARD LVDS [get_ports "CLK_DIFF_2_N"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 74 LVCMOS18 [get_ports "UART_GPIO_3"] #MGTs set_property PACKAGE_PIN AY38 [get_ports "124_REFCLK1_P"] set_property PACKAGE_PIN AY39 [get_ports "124_REFCLK1_N"] set_property PACKAGE_PIN BA40 [get_ports "124_REFCLK0_P"] set_property PACKAGE_PIN BA41 [get_ports "124_REFCLK0_N"] set_property PACKAGE_PIN AW40 [get_ports "124_TX3_P"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 75 PACKAGE_PIN AN45 [get_ports "126_RX0_P"] set_property PACKAGE_PIN AN46 [get_ports "126_RX0_N"] set_property PACKAGE_PIN AJ36 [get_ports "127_REFCLK1_P"] set_property PACKAGE_PIN AJ37 [get_ports "127_REFCLK1_N"] set_property PACKAGE_PIN AL36 [get_ports "127_REFCLK0_P"] set_property PACKAGE_PIN AL37 [get_ports "127_REFCLK0_N"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 76 PACKAGE_PIN AA41 [get_ports "129_TX0_N"] set_property PACKAGE_PIN AA45 [get_ports "129_RX0_P"] set_property PACKAGE_PIN AA46 [get_ports "129_RX0_N"] set_property PACKAGE_PIN U36 [get_ports "130_REFCLK1_P"] set_property PACKAGE_PIN U37 [get_ports "130_REFCLK1_N"] set_property PACKAGE_PIN W36 [get_ports "130_REFCLK0_P"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 77 PACKAGE_PIN BF5 [get_ports "224_TX0_P"] set_property PACKAGE_PIN BF4 [get_ports "224_TX0_N"] set_property PACKAGE_PIN BC2 [get_ports "224_RX0_P"] set_property PACKAGE_PIN BC1 [get_ports "224_RX0_N"] set_property PACKAGE_PIN AP11 [get_ports "225_REFCLK1_P"] set_property PACKAGE_PIN AP10 [get_ports "225_REFCLK1_N"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 78 PACKAGE_PIN AH1 [get_ports "227_RX1_N"] set_property PACKAGE_PIN AJ9 [get_ports "227_TX0_P"] set_property PACKAGE_PIN AJ8 [get_ports "227_TX0_N"] set_property PACKAGE_PIN AJ4 [get_ports "227_RX0_P"] set_property PACKAGE_PIN AJ3 [get_ports "227_RX0_N"] set_property PACKAGE_PIN AB11 [get_ports "228_REFCLK1_P"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 79 PACKAGE_PIN T2 [get_ports "230_RX1_P"] set_property PACKAGE_PIN T1 [get_ports "230_RX1_N"] set_property PACKAGE_PIN U9 [get_ports "230_TX0_P"] set_property PACKAGE_PIN U8 [get_ports "230_TX0_N"] set_property PACKAGE_PIN U4 [get_ports "230_RX0_P"] set_property PACKAGE_PIN U3 [get_ports "230_RX0_N"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 80 PACKAGE_PIN M2 [get_ports "231_RX1_P"] set_property PACKAGE_PIN M1 [get_ports "231_RX1_N"] set_property PACKAGE_PIN N9 [get_ports "231_TX0_P"] set_property PACKAGE_PIN N8 [get_ports "231_TX0_N"] set_property PACKAGE_PIN N4 [get_ports "231_RX0_P"] set_property PACKAGE_PIN N3 [get_ports "231_RX0_N"] VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...

  • Page 81: Overview

    System Controller Overview The Xilinx system controller is an ease-of-use application that runs on a Zynq-7000 AP SoC at power-up on the VCU1287 board. The system controller command line can be accessed through a serial communication terminal connection (115200-8-N-1) using the enhanced...

  • Page 82: Programmable Clocks Menu

    - Clock Menu- 1. Set VCU1287 Si570 Frequency 2. Set VCU1287 Si5368 Frequency 3. Save VCU1287 Clock Frequency to EEPROM 4. Restore VCU1287 Clock Frequency from EEPROM 5. View VCU1287 Saved Clocks in EEPROM 6. Set VCU1287 Clock Restore Options 7.
  • Page 83 Make sure J121 is set to position (2-3) DUT I2C DIS to isolate the DUT I2C signals and IMPORTANT: prevent bus contention. If contention occurs, the system controller will hang up while executing these commands. Option 3: Save VCU1287 Clock Frequency to EEPROM VCU1287 System Controller - Save Menu - ----------------------------- 1.
  • Page 84 NC1_LS=4 N2=1120000 N2_HS=4 N2_LS=280000 N31=40000 N32=22857 (The returned values include diagnostic information) Several seconds might elapse before the result is returned. Note: Option 5: View VCU1287 Saved Clocks in EEPROM Saved Clocks in EEPROM ----------------------------- Si570 User Clock: 200.00000000 MHz Si5328 MGT Clock: 200.00000000 MHz...

  • Page 85: Pmbus Menu

    This option returns to the menu level above. PMBus Menu The PMBus bus commands are used to read the voltage settings of the VCU1287 power rails controlled by the Maxim power system. Through the PMBus menu, these power rails can be read once or scanned continuously until stopped by a key press.
  • Page 86 (The returned values include configuration setting details.) Option 5: Get VCC_BRAM Voltage VCCBRAM = 0.950 V Unscaled Hex: MSB = 0x0F, LSB = 0x34 (The returned values include configuration setting details.) VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...
  • Page 87 UTIL2V5 = 2.500 V Unscaled Hex: MSB = 0x27, LSB = 0xFB (The returned values include diagnostic information.) Option 0: Return to Main Menu This option returns to the menu level above. VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...

  • Page 88: Power Monitoring Data Menu

    Appendix D: System Controller Power Monitoring Data Menu The VCU1287 includes the Texas Instrument INA226 power monitoring devices. The Power Monitoring Data menu, unlike the PMBus menu, provides both voltage and current monitoring for the MGT power modules, as well as the FPGA power rails.
  • Page 89 Appendix D: System Controller Select the device VCU1287 System Controller v1.0 - Select INA226 Menu - ----------------------------- 1. Select VCCINT Monitor 2. Select VCCAUX Monitor 3. Select VCCBRAM Monitor 4. Select VCCO_HP Monitor 5. Select VCCO_HR Monitor 6. Select MGTAVCC_R Monitor 7.

  • Page 90: Fpga Mezzanine Card (Fmc)

    Appendix D: System Controller FPGA Mezzanine Card (FMC) The VCU1287 board provides three FPGA mezzanine card (FMC) ANSI/VITA 57.1 expansion interfaces. All FMC mezzanine cards must host an IIC EEPROM that can be read out through the FMC menu. A raw hexadecimal display and a formatted version of the FMC EEPROM data are provided through the FMC menu.
  • Page 91 Appendix D: System Controller FMC Menu Options VCU1287 System Controller v1.0 - FMC Menu - ----------------------------- 1. Set FMC XMxxx CLOCKS 2. Read FMC1 IIC EEPROM 3. Read FMC2 IIC EEPROM 4. Read FMC3 IIC EEPROM 0. Return to Main Menu Identify the FMC module types and the FMC connecter number.
  • Page 92 - DC Output Records (three groups) If the FMC IIC EEPROM has not been programmed, ReadBuffer[000] - ReadBuffer[255] displays buffer contents = 0xFF and the Common Header reports “Invalid Format Version FF”. VCU1287 Characterization Board www.xilinx.com Send Feedback UG1121 (v1.0) December 11, 2015...

  • Page 93: Gpio Data Menu

    1. Get GPIO PL Data 2. Continuous Scan GPIO Readings 0. Return to Main Menu Option 1: Get GPIO PL Data The signals monitored with this option are currently not available in the VCU1287 board. ---------------------- FMC1_PRSNT = NO FMC2_PRSNT = NO...
  • Page 94 FPGA_IIC_BUSY = YES PMBUS_ALERT = YES Board EEPROM Data Menu The VCU1287 includes a QSPI memory device (N25Q128A) that is used to store the system controller firmware as well as additional test information VCU1287 System Controller v1.0 - EEPROM Menu - ----------------------------- 1.
  • Page 95 Appendix D: System Controller FPGA CONFIG Menu The system controller CONFIG menu is used to configure the VCU1287 UltraScale FPGA from an SD card (callout 8). One of sixteen bitstreams can be selected for use by the configuration engine by setting a binary encoded value on the system controller mode DIP...
  • Page 96 Topics include design assistance, advisories, and troubleshooting tips. References The most up to date information related to the VCU1287 board and its documentation is available on these websites: VCU1287 Characterization Kit VCU1287 Characterization Kit – Master Answer Record (Xilinx AR66056) These documents provide supplemental material useful with this guide: 1.
  • Page 97 Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...
  • Page 98 Programmable Logic IC Development Tools Click to view products by manufacturer: Xilinx Other Similar products are found below : DK-DEV-5SGXEA7N SLG4DVKADV 88980182 DEV-17526 DEV-17514 LCMXO3L-SMA-EVN 471-014 80-001005 iCE40UP5K- MDP-EVN ALTHYDRAC5GX ALTNITROC5GX 471-015 Hinj SnoMakrR10 DK-DEV-1SDX-P-A DK-DEV-1SDX-P-0ES DK-DEV- 1SGX-L-A DK-DEV-1SMC-H-A DK-DEV-1SMX-H-0ES DK-DEV-1SMX-H-A DK-DEV-4CGX150N DK-DEV-5CGTD9N DK-DEV-...

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