Xilinx Virtex-5 FPGA User Manual page 303

depending on the board design. The absolute maximum I/O limits might be exceeded
even if the clamp diode is active.
The IBIS models contain the voltage-current characteristics of the I/O drivers and clamp
diodes.
To verify overshoot and undershoot are within the I/O absolute maximum specifications,
Xilinx recommends proper I/O termination and performing IBIS simulation.
Source Termination and LVDCI_33
In general, the I/O drivers should match the board trace impedance to within ±10% to
minimize overshoot and undershoot. Source termination is often used for unidirectional
interfaces. The DCI feature has built-in source termination on all user output pins. It
compensates for impedance changes due to voltage and/or temperature fluctuations, and
can match the reference resistor values. Assuming the reference resistor values are the
same as the board trace impedance, the output impedance of the driver will closely match
with the board trace.
The LVDCI_33 standard is used to enable the DCI features for 3.3V I/O operations. As
shown in
termination function in Virtex-5 FPGA output drivers. The pull-up resistor connected to
VRN and the pull-down resistor connected to VRP determine the output impedance of all
the output drivers in the same bank. The
(DCI)"
Since the LVDCI_33 standard does not offer input termination, source termination must be
implemented on the driver side.
termination resistors to be incorporated on the external device side.
The total impedance of the LVTTL/LVCMOS driver added to the series termination
resistor R
undershoot. An IBIS simulation is advised for calculating the exact value needed for R
X-Ref Target - Figure 6-92
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Figure 6-92, the OBUF_LVDCI_33 primitive is used to implement the source
section has more details on using DCI.
must match the board trace impedance ±10 percent to minimize overshoot and
0
R
0
R + R
0 Driver
LVTTL/
Z = 50Ω (typical)
0
LVCMOS
Driver
External Device
Figure 6-92: Connecting LVTTL or LVCMOS Using the LVDCI_33 Standard
www.xilinx.com
Rules for Combining I/O Standards in the Same Bank
"Virtex-5 FPGA Digitally Controlled Impedance
Figure 6-92 shows the recommended external source
V = 3.3V
CCO
Z
0
IBUF_LVDCI_33
=
Virtex-5 FPGA
OBUF_LVDCI_33
V
CCO
R
REF
VRN
VRP
Any 3.3V
R
REF
I/O Device
Z
0
ug190_6_86_030506
.
0
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