Xilinx Virtex-5 FPGA User Manual page 5

Date Version
12/11/07 3.2
02/05/08 3.3
03/31/08 4.0
04/25/08 4.1
UG190 (v5.0) June 19, 2009
Chapter 1: Revised description in
XC5VLX20T, XC5VLX155, and XC5VLX155T devices to
Chapter 2: Added the XC5VLX20T, XC5VLX155, and XC5VLX155T devices to
Chapter 3: Revised "Clock Network Deskew," page
descriptions of CLKFBOUT and DEN in
CLKOUT[0:5]_PHASE and CLKFBOUT_MULT description in
Revised Figure 3-13 and Figure 3-14
Chapter 5: Added the XC5VLX20T, XC5VLX155, and XC5VLX155T devices to
Chapter 6: Clarified discussion of cascading across CMT tiles in
Changed the split termination to V
Chapter 7: Added to the descriptions of the
Attribute," and the "SIGNAL_PATTERN Attribute," page 330
Revised description in "Instantiating IDELAYCTRL Without LOC Constraints," page
340.
Chapter 8: Complete rewrite of the chapter. Many changes to descriptions, tables, and
figures.
Chapter 1: Updated discussion under
Chapter 3: Revised LOCKED description in
"Detailed VCO and Output Counter Waveforms," page
Chapter 5: Updated description of
Chapter 7: Updated description under
value to TRUE for HIGH_PERFORMANCE_MODE in
Chapter 8: Revised TRISTATE_WIDTH in
under "TRISTATE_WIDTH Attribute"
Methods," page 375.
Added the FXT platform to
Revised timing event description under
Revised "Dynamic Reconfiguration," page 73
Added CLKOUT[0:5]_DESKEW_ADJUST to
Corrected READ_WIDTH_B = 9 to WRITE_WIDTH_B = 9 in the block RAM usage rules
on page 114.
Revised "High-Speed Clock for Strobe-Based Memory Interfaces - OCLK," page
Corrected BITSLIP_ENABLE value from string to boolean in
Attributes," page 358.
Added the XC5VSX240T to
Revised Figure 1-21, page
Removed a pad notation from the ODDR output of
Removed the BUFG on the output of Figure 2-10.
Updated CLKOUT[0:5]_DESKEW_ADJUST description in
Revised equations Equation 3-5
Updated the notes in Table 4-16, page
Revised description of "Instantiating IDELAYCTRL with Location (LOC) Constraints,"
page 342.
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Revision
"Clock Gating for Power Savings," page
93. Removed note 2 and revised
Table 3-3, page
including waveforms.
= 0.9V in Figure 6-84, page
TT
"HIGH_PERFORMANCE_MODE
"I/O Clock Buffer - BUFIO" on page
Table 3-3, page
Figure 5-17.
"Clock Input - C" on page
Table 8-7, page
and added section on
Table 1-5, Table 2-1, and
Figure 1-21, page
to remove adjustment of PHASE_SHIFT.
Table 3-4, page
Table 1-5, Table 2-1, and
44.
Figure
and Equation 3-6.
145.
26. Added the
Table 1-5.
Table
96. Revised allowed value of
Table 3-4, page 98.
Table
"DCI Cascading."
292.
including Table
41.
96. Revised discussion under
103.
327. Updated default
Table 7-10, page 329.
374. Updated discussion
"OSERDES Clocking
Table 5-2.
44.
98.
"ISERDES_NODELAY
Table 5-2.
2-9.
Table 3-4, page 98.
Virtex-5 FPGA User Guide
2-1.
5-2.
7-10.
357.