Xilinx Virtex-5 FPGA User Manual page 6

Date Version
05/09/08 4.2
09/23/08 4.3
12/02/08 4.4
01/09/09 4.5
03/19/09 4.6
Virtex-5 FPGA User Guide
Revised clock routing resources in
Removed example Figure 2-10 on
Corrected note 1 in Table 4-5, page
Added "Legal Block RAM and FIFO Combinations," page
Clarified Note 7 in DCI in Virtex-5 Device I/O
in Banks 1 and 2.
Added the TXT platform to
Chapter 2: Revised "Reset Input - RST" on page 53
(Default)," page 66.
Chapter 3: Updated "Jitter Filter," page
Chapter 4: Updated "Write Modes" on page 117
page 119.
Chapter 6: Labeled all the DCI_18 standards consistently in
Replaced the link to the "Full Device SSO Calculator."
Chapter 8: Updated CLKB in
page 357.
Chapter 2: Changed "edge" to "half" in
on page 51, page 52, and page
Chapter 4: Added new text and equation to
1 to Table 4-19, page 148.
Chapter 5: Changed RAM#XM to RAM#M in
Chapter 6: Corrected PCI acronym definition in
Component Interconnect)," page
standard in "SSTL18_II_T_DCI (1.8V) Split-Thevenin Termination," page
Chapter 7: Added mode to caption of
Chapter 8: Added statement about shared resources between OCLK and CLK in
Speed Clock for Strobe-Based Memory Interfaces - OCLK," page
Chapter 4: Revised the paragraph below
Chapter 6: Added IBUFDS_DIFF_OUT to the list of primitive names for differential I/O
standards in "Virtex-5 FPGA SelectIO Primitives," page
"IBUFDS_DIFF_OUT," page
Chapter 7: In the Verilog code segment for bidirectional IODELAY on
the setting of RST.
Chapter 3: Added reference to the Virtex-5 FPGA Configuration Guide in
Primitive," page 93.
Chapter 4: In the second paragraph of
configuration" after READ_FIRST.
Chapter 5: In the third sentence of the second paragraph of
178, changed "slices" to "LUTs". Removed MC31 and SHIFTOUT from the bottom
SRL32 in Figure 5-19, page
Chapter 6: Inserted sentence about at least one I/O being configured as DCI to the
paragraph after Figure 6-4, page
www.xilinx.com
Revision
"BUFGCTRL to DCM," page
page 76.
124.
Standards. Master DCI is not supported
Table 1-5, Table 2-1, and Table
and
94.
and "Asynchronous Clocking" on
Table 8-1, page 355 and "High-Speed Clock Input - CLKB,"
IBUFG – Global Clock Input Buffer
53.
"Almost Empty Flag," page
Figure 5-32, page
"PCI-X, PCI-33, PCI-66 (Peripheral
247. Added to the description of the SSTL18_II_T_DCI
Figure 7-7, page 323
Equation 4-1
235.
"Write Modes," page
193.
220.
73.
171.
5-2.
"System-Synchronous Setting
Table 6-39 and Table
description
146. Added note
212.
293.
for clarification.
357.
on page 146.
233. Added new section
page 333, corrected
"PLL_ADV
117, added "in ECC
"Look-Up Table (LUT)," page
UG190 (v5.0) June 19, 2009
6-40.
"High-