Integration To Provide 1000Base-X Pcs And Pma Using A Rocketio Transceiver - Xilinx LogiCORE IP MAC v8.5 User Manual

Ug144 1-gigabit ethernet
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Ethernet 1000Base-X PCS/PMA or SGMII Core
Integration to Provide 1000BASE-X PCS and PMA using a RocketIO
Transceiver
Virtex-4 Devices
Figure 11-2
the GEMAC core to the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in
1000BASE-X mode with PMA using the device-specific RocketIO MGT transceiver.
1-Gigabit Ethernet
MAC
LogiCORE
gmii_rx_clk
gmii_txd[7:0]
gmii_rxd[7:0]
Figure 11-2: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
-- DISCONTINUED PRODUCT --
illustrates the connections and clock management logic required to interface
component_name_block
userclk2
(Block Level from example design)
(125 MHz)
Ethernet 1000BASE-X
PCS/PMA or SGMII
gtx_clk
gmii_txd[7:0]
gmii_tx_en
gmii_tx_en
gmii_tx_er
gmii_tx_er
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_dv
gmii_rx_er
gmii_rx_er
mdc
mdc
mdio_in
mdio_in
mdio_out
mdio_out
no
mdio_tri
mdio_tri
connection
using a RocketIO Transceiver
www.xilinx.com
brefclkp
(125 MHz)
IPAD
IPAD
brefclkn
(125 MHz)
BUFG
LogiCORE
userclk
userclk2
'0'
'0'
RocketIO I/F
Virtex-4
GT11CLK_MGT
MGTCLKP
MGTCLKN
synclk1
(125MHz)
SYNCLK1OUT
Virtex-4
GT11
RocketIO
TXOUTCLK1
REFCLK1
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
R
115

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