Xilinx Virtex-5 FPGA User Manual page 4

Date Version
02/02/07 3.0
09/11/07 3.1
Virtex-5 FPGA User Guide
Added the three SXT devices and the XC5VLX220T to
Chapter 4: Clarified wording in
Chapter 6: Added "DCI Cascading" on page
0.9 in Table 6-39.
Chapter 7: Revised OQ in
Chapter 8: "Clock Enable Inputs - CE1 and CE2" on page
Chapter 1: Added "Clock Gating for Power Savings" on page
page 30. Revised Figure 1-16, page
Chapter 2: Revised DCM reset and locking process in
Updated DO[2] description in
page 58. Revised the description for
"Output Clocks," page 65, updated
10, page 72. Added more steps to
M and D values on page 73. Updated
under Figure 2-20, page 87.
Chapter 3: Updated Figure 3-1, page
to "Phase Shift," page 95. Added rounding to
Revised CLKFBIN, CLKFBDCM, CLKFBOUT, RST, LOCKED, and added the REL pin
and note 2 to Table 3-3, page
Table 3-4, page 98. Removed general routing discussion from
Signals."Revised "Missing Input Clock or Feedback Clock"
to Figure 3-13. Corrected the Virtex-4 port mapping in
page 111.
Chapter 4: Revised and clarified
throughout. Clarified Readback limitation in
page 121. Edited "Set/Reset - SSR[A|B]," page
page 139. Revised latency values and added Note 1 to
"Cascading FIFOs to Increase Depth," page
Chapter 5: Clarified information about common control signals in a slice in
Elements" on page 178.
Chapter 6: Updated the DCI cascading guidelines on
"HSLVDCI Controlled Impedance Driver with Unidirectional Termination" since it is
not supported in software. Added note 3 to
introduction to "SSTL (Stub-Series Terminated Logic)," page
"DIFF_SSTL2_II_DCI, DIFF_SSTL18_II_DCI" on page
references in Figure 6-74, page
Standards in the Same Bank," page
"Overshoot/Undershoot," page
Chapter 7: Removed DDLY port from IDDR primitive
_PATTERN, DELAY_SRC, and REFCLK_FREQUENCY attributes to
page 329. Revised Figure 7-9, page
Clock From DCM" and updated REFCLK section in
Clarified introduction in "IDELAYCTRL Locations," page
Forwarding," page 347.
Chapter 8: Updated SR and O in
section for "BITSLIP Submodule," page
page 370.
www.xilinx.com
Revision
"Synchronous Clocking" on page
220. Changed V
Figure 7-27, page 349.
37.
Table 2-4, page 56. Changed the multiply value range on
"FACTORY_JF Attribute," page
Figure 2-7, page
Dynamic Reconfiguration
Figure 2-7, page
90. Add notes to
Equation 3-3
96. Added RESET_ON_LOSS_OF_LOCK attribute to
"Built-in Error Correction."
"Simple Dual-Port Block RAM" on
125. Added
157.
Table 6-17, page
282. Revised rules 2 and 3 in
298. Deleted of absolute maximum table from
302.
330. Removed Table 7-12: "Generating Reference
"IDELAYCTRL Ports" on page
Figure 8-2 and Table 8-1, page
366. Fixed typographical errors in
Table 1-5, Table 2-1, and Table
119.
for SSTL18_II_T_DCI to
REF
356.
26. Revised Figure 1-2,
"Reset Input - RST," page
61. Revised
74, and added a BUFG to Figure 2-
(DRPs) when loading new
74. Revised bulleted descriptions
Table 3-2, page 93. Added a note
through Equation 3-6.
"PLL Clock Input
section. Added waveforms
Figure 3-17 and Table 3-8,
Edited WE signal
"Block RAM Retargeting,"
Table 4-16, page 145. Updated
"Storage
page 223. Removed references to
256. Clarified the
274. Revised
275. Fixed DIFF_SSTL2_II
"Rules for Combining I/O
page 321. Added the SIGNAL
Table 7-10,
339. Changed ODDR
355. Updated the entire
Figure 8-14,
UG190 (v5.0) June 19, 2009
5-2.
53.
338.
"Clock