Xilinx Virtex-5 FPGA User Manual page 32

Chapter 1: Clock Resources
BUFGCE and BUFGCE_1
Unlike BUFG, BUFGCE is a clock buffer with one clock input, one clock output and a clock
enable line. This primitive is based on BUFGCTRL with some pins connected to logic High
or Low.
constraint is available for BUFGCE and BUFGCE_1.
X-Ref Target - Figure 1-5
The switching condition for BUFGCE is similar to BUFGCTRL. If the CE input is Low prior
to the incoming rising clock edge, the following clock pulse does not pass through the
clock buffer, and the output stays Low. Any level change of CE during the incoming clock
High pulse has no effect until the clock transitions Low. The output stays Low when the
clock is disabled. However, when the clock is being disabled it completes the clock High
pulse.
Since the clock enable line uses the CE pin of the BUFGCTRL, the select signal must meet
the setup time requirement. Violating this setup time may result in a glitch.
illustrates the timing diagram for BUFGCE.
X-Ref Target - Figure 1-6
BUFGCE_1 is similar to BUFGCE, with the exception of its switching condition. If the CE
input is Low prior to the incoming falling clock edge, the following clock pulse does not
pass through the clock buffer, and the output stays High. Any level change of CE during
the incoming clock Low pulse has no effect until the clock transitions High. The output
stays High when the clock is disabled. However, when the clock is being disabled it
completes the clock Low pulse.
32
Figure 1-5 illustrates the relationship of BUFGCE and BUFGCTRL. A LOC
BUFGCE
CE
I
Figure 1-5: BUFGCE as BUFGCTRL
BUFGCE(I)
BUFGCE(CE)
BUFGCE(O)
Figure 1-6: BUFGCE Timing Diagram
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BUFGCE as BUFGCTRL
IGNORE1
V
DD
CE1
GND
S1
GND
I1
V
DD
O
I0
I
S0
V
DD
CE0
CE
IGNORE0
GND
T
BCCCK_CE
T
BCCKO_O
O
ug190_1_05_032206
Figure 1-6
ug190_1_06_032206
Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009