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The V850E/IA1 is provided with an external bus interface function by which external I/O and memories, such as
ROM and RAM, can be connected.
4.1 Features
• 16-bit/8-bit data bus sizing function
• 8-space chip select function
• Wait function
• Programmable wait function, through which up to 7 wait states can be inserted for each memory block
• External wait function via WAIT pin
• Idle state insertion function
• Bus hold function
• External device connection enabled via bus control/port alternate function pins
4.2 Bus Control Pins
The following pins are used for connection to external devices.
Bus Control Pin (Function When in Control Mode)
Address/data bus (AD0 to AD15)
Address bus (A16 to A23)
Chip select (CS0 to CS7)
Read/write control (LWR/UWR, RD, ASTB)
External wait control (WAIT)
Internal system clock (CLKOUT)
Bus hold control (HLDRQ, HLDAK)
Remark In the case of single-chip mode 1 and ROMless modes 0 and 1, when the system is reset, each bus
control pin becomes unconditionally valid.
4.2.1 Pin status during internal ROM, internal RAM, and on-chip peripheral I/O access
When the internal ROM and RAM are accessed, both the address bus and address/data bus become undefined.
The external bus control signal becomes inactive.
When on-chip peripheral I/O are accessed, both the address bus and address/data bus output the addresses of the
on-chip peripheral I/O currently being accessed. No data is output. The external bus control signal becomes inactive.
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CHAPTER 4 BUS CONTROL FUNCTION
User's Manual U14492EJ3V0UD
Function When in Port Mode
PDL0 to PDL15 (Port DL)
PDH0 to PDH7 (Port DH)
PCS0 to PCS7 (Port CS)
PCT0, PCT1, PCT4, PCT6
(Port CT)
PCM0 (Port CM)
PCM1 (Port CM)
PCM2, PCM3 (Port CM)
Register for Port/Control
Mode Switching
PMCDL
PMCDH
PMCCS
PMCCT
PMCCM
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