6.4.2 DMAC bus cycle state transition
Except for the block transfer mode, each time the processing for a DMA transfer is completed, the bus
mastership is released.
Figure 6-12: DMAC Bus Cycle (Two-Cycle Transfer) State Transition
Chapter 6 DMA Functions (DMA Controller)
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TI
T0
T1R
T2R
T2RI
T1W
T2W
TE
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