Px Port Mode Select Register; Px Port Function Select Register; P Port Clock Control Register - Epson S1C17M12 Technical Manual

Bits 15–8 Reserved
Bits 7–0 PxCHATEN[7:0]
These bits enable/disable the chattering filter function.
1 (R/W): Enable (The chattering filter is used.)
0 (R/W): Disable (The chattering filter is bypassed.)

Px Port Mode Select Register

Register name Bit
PxMODSEL 15–8 –
7–0 PxSEL[7:0]
*1: The bit configuration differs depending on the port group.
*2: The initial value may be changed by the port.
Bits 15–8 Reserved
Bits 7–0 PxSEL[7:0]
These bits select whether each port is used for the GPIO function or a peripheral I/O function.
1 (R/W): Use peripheral I/O function
0 (R/W): Use GPIO function

Px Port Function Select Register

Register name Bit
PxFNCSEL 15–14 Px7MUX[1:0]
13–12 Px6MUX[1:0]
11–10 Px5MUX[1:0]
9–8 Px4MUX[1:0]
7–6 Px3MUX[1:0]
5–4 Px2MUX[1:0]
3–2 Px1MUX[1:0]
1–0 Px0MUX[1:0]
*1: The bit configuration differs depending on the port group.
*2: The initial value may be changed by the port.
Bits 15–14 Px7MUX[1:0]
: :
Bits 1–0 Px0MUX[1:0]
These bits select the peripheral I/O function to be assigned to each port pin.
This selection takes effect when the PxMODSEL.PxSELy bit = 1.

P Port Clock Control Register

Register name Bit
PCLK 15–9 –
8
7–4 CLKDIV[3:0]
3–2 KRSTCFG[1:0]
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
Bit name Initial
0x00
0x00
Bit name Initial
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Table 6.6.1 Selecting Peripheral I/O Function
PxFNCSEL.PxyMUX[1:0] bits
0x3
0x2
0x1
0x0
Bit name Initial
0x00
DBRUN 0
0x0
0x0
0x0
Seiko Epson Corporation
Reset R/W
– R –
H0 R/W
Reset R/W
H0 R/W –
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
Peripheral I/O function
Function 3
Function 2
Function 1
Function 0
Reset R/W
– R –
H0 R/WP
H0 R/WP
H0 R/WP
H0 R/WP
6 I/O PORTS (PPORT)
Remarks
Remarks
Remarks
6-9