Px Port Function Select Register; P Port Clock Control Register - Epson S1C31W65 Technical Manual

Bits 7–0 PxSEL[7:0]
These bits select whether each port is used for the GPIO function or a peripheral I/O function.
1 (R/W): Use peripheral I/O function
0 (R/W): Use GPIO function

Px Port Function Select Register

Register name Bit
PPORTPxFNCSEL 15–14 Px7MUX[1:0]
13–12 Px6MUX[1:0]
11–10 Px5MUX[1:0]
9–8 Px4MUX[1:0]
7–6 Px3MUX[1:0]
5–4 Px2MUX[1:0]
3–2 Px1MUX[1:0]
1–0 Px0MUX[1:0]
*1: The bit configuration differs depending on the port group.
*2: The initial value may be changed by the port.
Bits 15–14 Px7MUX[1:0]
: :
Bits 1–0 Px0MUX[1:0]
These bits select the peripheral I/O function to be assigned to each port pin.
PPORTPxFNCSEL.PxyMUX[1:0] bits
This selection takes effect when the PPORTPxMODSEL.PxSELy bit = 1.

P Port Clock Control Register

Register name Bit
PPORTCLK 15–9 –
8
7–4 CLKDIV[3:0]
3–2 KRSTCFG[1:0]
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the PPORT operating clock is supplied during debugging or not.
1 (R/WP): Clock supplied during debugging
0 (R/WP): No clock supplied during debugging
Bits 7–4 CLKDIV[3:0]
These bits select the division ratio of the PPORT operating clock (chattering filter clock).
Bits 3–2 KRSTCFG[1:0]
These bits configure the key-entry reset function.
PPORTCLK.KRSTCFG[1:0] bits
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
Bit name Initial
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Table 7.6.1 Selecting Peripheral I/O Function
0x3
0x2
0x1
0x0
Bit name Initial
0x00
DBRUN 0
0x0
0x0
0x0
Table 7.6.2 Key-Entry Reset Function Settings
0x3
0x2
0x1
0x0
Seiko Epson Corporation
Reset R/W
H0 R/W –
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
Peripheral I/O function
Function 3
Function 2
Function 1
Function 0
Reset R/W
– R –
H0 R/WP
H0 R/WP
H0 R/WP
H0 R/WP
key-entry reset
Reset when P0[3:0] inputs = all low
Reset when P0[2:0] inputs = all low
Reset when P0[1:0] inputs = all low
Disable
7 I/O PORTS (PPORT)
Remarks
Remarks
7-9