I2C Ch.n Own Address Register; I2C Ch.n Control Register - Epson S1C31W65 Technical Manual

15 I 2 C (I2C)
Bits 6–0 BRT[6:0]
These bits set the I2C Ch.n transfer rate for master mode. For more information, refer to "Baud Rate
Generator."
Notes: • The I2C_nBR register settings can be altered only when the I2C_nCTL.MODEN bit = 0.
• Be sure to avoid setting the I2C_nBR register to 0.

I2C Ch.n Own Address Register

Register name Bit
I2C_nOADR 15–10 –
9–0 OADR[9:0]
Bits 15–10 Reserved
Bits 9–0 OADR[9:0]
These bits set the own address for slave mode.
The I2C_nOADR.OADR[9:0] bits are effective in 10-bit address mode (I2C_nMOD.OADR10 bit = 1),
or the I2C_nOADR.OADR[6:0] bits are effective in 7-bit address mode (I2C_nMOD.OADR10 bit =
0).
Note: The I2C_nOADR register settings can be altered only when the I2C_nCTL.MODEN bit = 0.

I2C Ch.n Control Register

Register name Bit
I2C_nCTL 15–8 –
7–6 –
5
4
3
2
1
0
Bits 15–6 Reserved
Bit 5 MST
This bit selects the I2C Ch.n operating mode.
1 (R/W): Master mode
0 (R/W): Slave mode
Bit 4 TXNACK
This bit issues a request for sending a NACK at the next responding.
1 (W): Issue a NACK.
0 (W): Ineffective
1 (R): On standby or during sending a NACK
0 (R): NACK has been sent.
This bit is automatically cleared after a NACK has been sent.
Bit 3 TXSTOP
This bit issues a STOP condition in master mode. This bit is ineffective in slave mode.
1 (W): Issue a STOP condition.
0 (W): Ineffective
1 (R): On standby or during generating a STOP condition
0 (R): STOP condition has been generated.
This bit is automatically cleared when the bus free time (t
elapsed after the STOP condition has been generated.
15-20
Bit name Initial
0x00
0x000
Bit name Initial
0x00
0x0
MST 0
TXNACK 0
TXSTOP 0
TXSTART 0
SFTRST 0
MODEN 0
Seiko Epson Corporation
Reset R/W
– R –
H0 R/W
Reset R/W
– R –
– R
H0 R/W
H0/S0 R/W
H0/S0 R/W
H0/S0 R/W
H0 R/W
H0 R/W
defined in the I
BUF
S1C31W65 TECHNICAL MANUAL
Remarks
Remarks
C Specifications) has
2
(Rev. 1.1)