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13 I
2
C (I2C)
I2C Ch.n Mode Register
Register name
Bit
I2CnMOD
15–8 –
7–3 –
2
1
0
Bits 15–3 Reserved
Bit 2
OADR10
This bit sets the number of own address bits for slave mode.
1 (R/W): 10-bit address
0 (R/W): 7-bit address
Bit 1
GCEN
This bit sets whether to respond to master general calls in slave mode or not.
1 (R/W): Respond to general calls.
0 (R/W): Do not respond to general calls.
Bit 0
Reserved
Note: The I2CnMOD register settings can be altered only when the I2CnCTL.MODEN bit = 0.
I2C Ch.n Baud-Rate Register
Register name
Bit
I2CnBR
15–8 –
7
6–0 BRT[6:0]
Bits 15–7 Reserved
Bits 6–0
BRT[6:0]
These bits set the I2C Ch.n transfer rate for master mode. For more information, refer to "Baud Rate
Generator."
Notes: • The I2CnBR register settings can be altered only when the I2CnCTL.MODEN bit = 0.
• Be sure to avoid setting the I2CnBR register to 0.
I2C Ch.n Own Address Register
Register name
Bit
I2CnOADR
15–10 –
9–0 OADR[9:0]
Bits 15–10 Reserved
Bits 9–0
OADR[9:0]
These bits set the own address for slave mode.
The I2CnOADR.OADR[9:0] bits are effective in 10-bit address mode (I2CnMOD.OADR10 bit = 1),
or the I2CnOADR.OADR[6:0] bits are effective in 7-bit address mode (I2CnMOD.OADR10 bit = 0).
Note: The I2CnOADR register settings can be altered only when the I2CnCTL.MODEN bit = 0.
13-18
Bit name
Initial
0x00
0x00
OADR10
0
GCEN
0
–
0
Bit name
Initial
0x00
–
0
0x7f
Bit name
Initial
0x00
0x000
Seiko Epson Corporation
Reset
R/W
–
R
–
–
R
H0
R/W
H0
R/W
–
R
Reset
R/W
–
R
–
–
R
H0
R/W
Reset
R/W
–
R
–
H0
R/W
S1C17M12/M13 TECHNICAL MANUAL
Remarks
Remarks
Remarks
(Rev. 1.2)
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