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7.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell
The over voltage tolerant fail-safe type I/O cell allows interfacing without passing unnecessary current even if a
voltage exceeding V
is applied to the port. Also unnecessary current is not consumed when the port is externally
DD
biased without supplying V
mum operating power supply voltage to the port.
7.2.3 Pull-Up/Pull-Down
The GPIO port has a pull-up/pull-down function. Either pull-up or pull-down may be selected for each port indi-
vidually. This function may also be disabled for the port that does not require pulling up/down.
When the port level is switched from low to high through the pull-up resistor included in the I/O cell or from high
to low through the pull-down resistor, a delay will occur in the waveform rising/falling edge depending on the time
constant by the pull-up/pull-down resistance and the pin load capacitance. The rising/falling time is commonly de-
termined by the following equation:
t
= -R
× (C
+ C
PR
INU
IN
t
= -R
× (C
+ C
PF
IND
IN
Where
t
:
Rising time (port level = low → high) [second]
PR
t
:
Falling time (port level = high → low) [second]
PF
V
:
High level Schmitt input threshold voltage [V]
T+
V
:
Low level Schmitt input threshold voltage [V]
T-
R
/R
: Pull-up/pull-down resistance [W]
INU
IND
C
:
Pin capacitance [F]
IN
C
:
Parasitic capacitance on the board [F]
BOARD
7.2.4 CMOS Output and High Impedance State
The I/O cells except for analog output can output signals in the V
put into high-impedance (Hi-Z) state.
7.3 Clock Settings
7.3.1 PPORT Operating Clock
When using the chattering filter for entering external signals to PPORT, the PPORT operating clock CLK_PPORT
must be supplied to PPORT from the clock generator.
The CLK_PPORT supply should be controlled as in the procedure shown below.
1. Enable the clock source in the clock generator if it is stopped (refer to "Clock Generator" in the "Power Supply,
Reset, and Clocks" chapter).
2. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)
3. Set the following PPORTCLK register bits:
- PPORTCLK.CLKSRC[1:0] bits
- PPORTCLK.CLKDIV[3:0] bits
4. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection)
Settings in Step 3 determine the input sampling time of the chattering filter.
7.3.2 Clock Supply in SLEEP Mode
When using the chattering filter function during SLEEP mode, the PPORT operating clock CLK_PPORT must be
configured so that it will keep suppling by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_PPORT clock
source.
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
. However, be sure to avoid applying a voltage exceeding the recommended maxi-
DD
) × ln(1 - V
/V
)
BOARD
T+
DD
) × ln(1 - V
/V
)
BOARD
T-
DD
Seiko Epson Corporation
(Eq. 7.1)
and V
levels. Also the GPIO ports may be
DD
SS
(Clock source selection)
(Clock division ratio selection = Clock frequency setting)
7 I/O PORTS (PPORT)
7-3
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