Data Length Counter Clock Settings - Epson S1C17001 Technical Manual

21 REMOTE CONTROLLER (REMC)

21.4 Data Length Counter Clock Settings

The data length counter is an 8-bit counter for setting data lengths when transmitting data.
When a value corresponding to the data pulse width is written during data transmission, the data length counter be-
gins counting down from that value, generating an underflow interrupt factor and halting when the counter reaches 0.
The subsequent transmit data is set using this interrupt.
This counter is also used for data receiving, enabling measurement of the receive data length. Interrupts can be gen-
erated at the input signal rising or falling edges when receiving data. The data pulse length can be obtained from the
difference between data pulses by setting the data length counter to 0xff using the interrupt when the input changes
and by reading out the count value when a subsequent interrupt occurs due to input changes.
This data length counter count clock also uses a prescaler output clock and can select one of 15 different types. The
prescaler output clock is selected by the control bit LCCLK[3:0] (D[3:0]/REMC_PSC register) provided separately
to the carrier generation clock.
∗ LCCLK[3:0]: Length Counter Clock Select Bits in the REMC Prescaler Clock Select (REMC_PSC) Register
(D[3:0]/0x5341)
LCCLK[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
The data length counter can count up to 256. The count clock should be selected to ensure that the data length fits
within this range.
272
Table 21.4.1: Data length counter clock selection
Prescaler output clock
Reserved
PCLK-1/16384
PCLK-1/8192
PCLK-1/4096
PCLK-1/2048
PCLK-1/1024
PCLK-1/512
PCLK-1/256
EPSON
LCCLK[3:0] Prescaler output clock
0x7 PCLK-1/128
0x6
0x5
0x4
0x3
0x2
0x1
0x0
S1C17001 TECHNICAL MANUAL
PCLK-1/64
PCLK-1/32
PCLK-1/16
PCLK-1/8
PCLK-1/4
PCLK-1/2
PCLK-1/1
(Default: 0x0)