C (I2C); Overview - Epson S1C17M20 Technical Manual

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14 I

C (I2C)

14.1 Overview

The I2C is a subset of the I
• Functions as an I C bus master (single master) or a slave device.
2
• Supports standard mode (up to 100 kbit/s) and fast mode (up to 400 kbit/s).
• Supports 7-bit and 10-bit address modes.
• Supports clock stretching.
• Includes a baud rate generator for generating the clock in master mode.
• No clock source is required to run the I2C in slave mode, as it can run with the I
• Slave mode is capable of being operated in SLEEP mode allowing wake-up by an interrupt when an address
match is detected.
• Master mode supports automatic bus clear sending function.
• Can generate receive buffer full, transmit buffer empty, and other interrupts.
Figure 14.1.1 shows the I2C configuration.
Table 14.1.1 I2C Channel Configuration of S1C17M20/M21/M22/M23/M24/M25
Item
Number of channels
I2C Ch.n
Interrupt controller
BYTEENDIE
GCIE
NACKIE
STOPIE
STARTIE
ERRIE
RBFIE
TBEIE
SFTRST
OADR10
OADR[9:0]
GCEN
MST
TXNACK
TXSTART
TXSTOP
CLKSRC[1:0]
CLKDIV[1:0]
Clock generator
DBRUN
MODEN
CLK_I2Cn
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
2 C bus interface. The features of the I2C are listed below.
S1C17M20/M23
24-pin package
Receive data buffer
Transmit data buffer
Interrupt
BYTEENDIF
control circuit
NACKIF
STOPIF
STARTIF
ERRIF
RBFIF
TBEIF
Transmit/receive
BRT[6:0]
Figure 14.1.1 I2C Configuration
Seiko Epson Corporation
S1C17M21/M24
32-pin package
1 channel (Ch.0)
RXD[7:0]
TXD[7:0]
GCIF
control circuit
Slave mode
controller
Master mode
controller
Baud rate
generator
14 I
2 C bus signals only.
S1C17M22/M25
Shift register
Shift register
V
SS
SDALOW
SCLLOW
BSY
TR
SCLO
V
SS
2 C (I2C)
SDAn
SCLn
14-1