C (I2C); Overview - Epson S1C31W65 Technical Manual

15 I

C (I2C)

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15.1 Overview

The I2C is a subset of the I
• Functions as an I C bus master (single master) or a slave device.
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• Supports standard mode (up to 100 kbit/s) and fast mode (up to 400 kbit/s).
• Supports 7-bit and 10-bit address modes.
• Supports clock stretching.
• Includes a baud rate generator for generating the clock in master mode.
• No clock source is required to run the I2C in slave mode, as it can run with the I
• Slave mode is capable of being operated in SLEEP mode allowing wake-up by an interrupt when an address
match is detected.
• Master mode supports automatic bus clear sending function.
• Can generate receive buffer full, transmit buffer empty, and other interrupts.
• Can issue a DMA transfer request when a receive buffer full or a transmit buffer empty occurs.
• The input filter for the SDA and SCL inputs does not comply with the standard for removing noise spikes less
than 50 ns.
Figure 15.1.1 shows the I2C configuration.
Item
Number of channels
I2C Ch.n
DMA
controller
TBEDMAENx
RBFDMAENx
CPU
BYTEENDIE
GCIE
NACKIE
STOPIE
STARTIE
ERRIE
RBFIE
TBEIE
SFTRST
OADR10
OADR[9:0]
GCEN
MST
TXNACK
TXSTART
TXSTOP
CLKSRC[1:0]
CLKDIV[1:0]
Clock
DBRUN
generator
MODEN
CLK_I2Cn
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
C bus interface. The features of the I2C are listed below.
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Table 15.1.1 I2C Channel Configuration of S1C31W65
Receive data buffer
DMA request
control circuit
Transmit data buffer
BYTEENDIF
Interrupt NACKIF
STOPIF
control circuit
STARTIF
ERRIF
Transmit/receive
BRT[6:0]
Figure 15.1.1 I2C Configuration
Seiko Epson Corporation
S1C31W65
2 channels (Ch.0 and Ch.1)
RXD[7:0]
TXD[7:0]
GCIF
RBFIF
TBEIF
control circuit
Slave mode
controller
Master mode
controller
Baud rate
generator
15 I
C bus signals only.
2
Shift register
Shift register
V
SS
SDALOW
SCLLOW
BSY
TR
SCLO
V
SS
2 C (I2C)
SDAn
SCLn
15-1