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13
Serial Interface
Note: The S1C63003 has no serial interface included.
13.1
Configuration of Serial interface
The S1C63004/008/016 has a built-in 8-bit clock synchronous type serial interface. The CPU, via the 8-bit shift reg-
ister, can read the serial input data from the SIN terminal. Moreover, via the same 8-bit shift register, it can convert
parallel data to serial data and output it to the SOUT terminal. The synchronous clock for serial data input/output may
be set by software any one of seven types of master mode (internal clock mode: when the S1C63004/008/016 is to
be the master for serial input/output) and one type of slave mode (external clock mode: when the S1C63004/008/016
is to be the slave for serial input/output).
The configuration of the serial interface is shown in Figure 13.1.1.
SIN
(P32)
f
OSC1
Clock
f
OSC3
manager
Programmable
timer 1
SIFCKS[2:0]
SIF clock selection
Interrupt request
SCLK
(P30)
13.2
Serial interface Terminals
The following shows the terminals used in the serial interface and their functions:
SCLK (P30)
Inputs or outputs the serial clock. By writing "1" to the ESIF register to enable the serial interface, the P30
terminal is switched to the SCLK terminal. In master mode, the SCLK terminal is configured for output and it
outputs the synchronous clock generated in the IC during data transfer. In slave mode, the SCLK terminal inputs
the synchronous clock output by the external master device.
SIN (P32)
Inputs serial data. By writing "1" to the ESIF register to enable the serial interface, the P32 terminal is switched
to the SIN terminal.
SOUT (P31)
Outputs serial data. By default, the SOUT terminal is not enabled even if "1" is written to the ESIF register. When
using the SOUT output, write "1" to the ESOUT register.
If serial input only is required, the P31 terminal can be used as an I/O port terminal.
SRDY (P33)
In slave mode, this terminal outputs the SRDY signal to the master device to indicate that the serial interface is
ready to transfer. By default, the SRDY terminal is not enabled even if the serial interface is set to slave mode.
When using the SRDY output in slave mode, write "1" to the ENCS and ESREADY registers.
SS (P33)
Inputs the SS (Slave Select) signal when the S1C63004/008/016 is used as an SPI slave device. When using the
SS input, write "1" to ENCS and write "0" to ESREADY.
S1C63003/004/008/016 TeChniCal Manual
(Rev. 1.1)
[S1C63004/008/016]
Data bus
8-bit shift register
SD[7:0]
SCPS[1:0]
Clock format selection
Clock
Interrupt control
control
Figure 13.
1.1 Configuration of serial interface
Seiko epson Corporation
Output
latch
SDP
Data I/O permutation
ESIF
SIF enable (P3x)
SCTRG
SIF clock trigger
ENCS
SRDY_SS enable (P33)
ESREADY
SRDY_SS function selection
SMOD
Mode selection
Transfer
mode control
13 SeRial inTeRFaCe
SOUT
(P31)
ESOUT
SOUT enable
SS
or
SRDY
(P33)
Serial interface
13-1
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