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12.3.3 Clock Supply in DEBUG Mode
The CLK_UARTn supply during DEBUG mode should be controlled using the UAnCLK.DBRUN bit.
The CLK_UARTn supply to the UART Ch.n is suspended when the CPU enters DEBUG mode if the UAnCLK.
DBRUN bit = 0. After the CPU returns to normal mode, the CLK_UARTn supply resumes. Although the UART
Ch.n stops operating when the CLK_UARTn supply is suspended, the output pin and registers retain the status be-
fore DEBUG mode was entered. If the UAnCLK.DBRUN bit = 1, the CLK_UARTn supply is not suspended and
the UART Ch.n will keep operating in DEBUG mode.
12.3.4 Baud Rate Generator
The UART includes a baud rate generator to generate the transfer (sampling) clock. The transfer rate is determined
by the UAnBR.BRT[7:0] and UAnBR.FMD[3:0] bit settings. Use the following equations to calculate the setting
values for obtaining the desired transfer rate.
CLK_UART
bps = — — — — — — — — — — — — — — —
{(BRT + 1) × 16 + FMD}
Where
CLK_UART: UART operating clock frequency [Hz]
bps:
Transfer rate [bit/s]
BRT:
UAnBR.BRT[7:0] setting value (0 to 255)
FMD:
UAnBR.FMD[3:0] setting value (0 to 15)
For the transfer rate range configurable in the UART, refer to "UART Characteristics, Transfer baud rates U
and U
" in the "Electrical Characteristics" chapter.
BRT2
12.4 Data Format
The UART allows setting of the data length, stop bit length, and parity function. The start bit length is fixed at one
bit.
Data length
With the UAnMOD.CHLN bit, the data length can be set to seven bits (UAnMOD.CHLN bit = 0) or eight bits
(UAnMOD.CHLN bit = 1).
Stop bit length
With the UAnMOD.STPB bit, the stop bit length can be set to one bit (UAnMOD.STPB bit = 0) or two bits
(UAnMOD.STPB bit = 1).
Parity function
The parity function is configured using the UAnMOD.PREN and UAnMOD.PRMD bits.
UAnMOD.PREN bit
S1C17W22/W23 TECHNICAL MANUAL
(Rev. 1.3)
BRT =
Table 12.4.1 Parity Function Setting
UAnMOD.PRMD bit
1
1
1
0
0
*
Seiko Epson Corporation
(
CLK_UART
— — — — — — — — - FMD - 16
bps
Parity function
Odd parity
Even parity
Non parity
12 UART (UART)
)
÷ 16
(Eq. 12.1)
BRT1
12-3
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