Clock Supply In Sleep Mode; Clock Supply In Debug Mode; Baud Rate Generator; Data Format - Epson S1C17M20 Technical Manual

12.3.2 Clock Supply in SLEEP Mode

When using the UART3 during SLEEP mode, the UART3 operating clock CLK_UART3_n must be configured so
that it will keep supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_UART3_n clock source.

12.3.3 Clock Supply in DEBUG Mode

The CLK_UART3_n supply during DEBUG mode should be controlled using the UAnCLK.DBRUN bit.
The CLK_UART3_n supply to the UART3 Ch.n is suspended when the CPU enters DEBUG mode if the UAnCLK.
DBRUN bit = 0. After the CPU returns to normal mode, the CLK_UART3_n supply resumes. Although the UART3
Ch.n stops operating when the CLK_UART3_n supply is suspended, the output pin and registers retain the status
before DEBUG mode was entered. If the UAnCLK.DBRUN bit = 1, the CLK_UART3_n supply is not suspended
and the UART3 Ch.n will keep operating in DEBUG mode.

12.3.4 Baud Rate Generator

The UART3 includes a baud rate generator to generate the transfer (sampling) clock. The transfer rate is determined
by the UAnMOD.BRDIV, UAnBR.BRT[7:0], and UAnBR.FMD[3:0] bit settings. Use the following equations to
calculate the setting values for obtaining the desired transfer rate.
CLK_UART3
bps = —————————
BRT + 1
———— + FMD
BRDIV
Where
bps: Transfer rate [bit/s]
CLK_UART3: UART3 operating clock frequency [Hz]
Baud rate division ratio (1/16 or 1/4) * Selected by the UAnMOD.BRDIV bit
BRDIV:
BRT: UAnBR.BRT[7:0] setting value (0 to 255)
FMD: UAnBR.FMD[3:0] setting value (0 to 15)
For the transfer rate range configurable in the UART3, refer to "UART Characteristics, Transfer baud rates U
and U " in the "Electrical Characteristics" chapter.
BRT2

12.4 Data Format

The UART3 allows setting of the data length, stop bit length, and parity function. The start bit length is fixed at one
bit.
Data length
With the UAnMOD.CHLN bit, the data length can be set to seven bits (UAnMOD.CHLN bit = 0) or eight bits
(UAnMOD.CHLN bit = 1).
Stop bit length
With the UAnMOD.STPB bit, the stop bit length can be set to one bit (UAnMOD.STPB bit = 0) or two bits
(UAnMOD.STPB bit = 1).
Parity function
The parity function is configured using the UAnMOD.PREN and UAnMOD.PRMD bits.
UAnMOD.PREN bit
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
BRT = BRDIV ×
Table 12.4.1 Parity Function Setting
UAnMOD.PRMD bit
1 1
1 0
0
*
Seiko Epson Corporation
( )
CLK_UART3
—————— - FMD - 1
bps
Parity function
Odd parity
Even parity
Non parity
12 UART (UART3)
(Eq. 12.1)
BRT1
12-3