Bus Control Pins; Pin Status When Internal Rom, Internal Ram, Or Peripheral I/O Is Accessed; Pin Status In Each Operation Mode; Table 5-1: Bus Control Pins (Multiplexed Bus) - NEC V850E/RS1 User Manual

5.2 Bus Control Pins

The pins used to connect an external device are listed in the table below.
Bus Control Pin
AD0 to AD15
WAIT
CLKOUT
CS0, CS1
WR0, WR1
RD
ASTB
HLDRQ
HLDAK

5.2.1 Pin status when internal ROM, internal RAM, or peripheral I/O is accessed

Table 5-2: Pin Status When Internal ROM, Internal RAM, or Peripheral I/O Is Accessed

5.2.2 Pin status in each operation mode

For the pin status of the V850E/RS1 in each operation mode, refer to 2.3 "Description of Pin Func-
tions" on page 45.
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Chapter 5 Bus Control Function

Table 5-1: Bus Control Pins (Multiplexed Bus)

Alternate-Function Pin
PDL0 to PDL15
PCM0
PCM1
PCS0, PCS1
PCT0, PCT1
PCT4
PCT6
PCM3
PCM2
Access Destination Address Bus
AD0 to AD15 undefined
User's Manual U16702EE3V2UD00
I/O
I/O Address/data bus
Input External wait control
Output Internal system clock
Output Chip select signal
Output Write strobe signal
Output Read strobe signal
Output Address strobe signal
Input
Bus hold control
Output
Data Bus
Hi-Z
Function
Control Signal
Inactive