C Bus Definitions And Control Methods - NEC V850ES/SA2 UPD703201 Manual

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12.4.4 I

C bus definitions and control methods

The following section describes the I
The transfer timing for the "start condition", "data", and "stop condition" output via the I
shown below.
SCL
SDA
Start Address
condition
The master device outputs the start condition, slave address, and stop condition.
The acknowledge signal (ACK) can be output by either the master or slave device (normally, it is output by the device
that receives 8-bit data).
The serial clock (SCL) is continuously output by the master device. However, in the slave device, SCL's low-level
period can be extended and a wait can be inserted.
(1) Start condition
A start condition is met when the SCL pin is at high level and the SDA pin changes from high level to low level.
The start conditions for the SCL pin and SDA pin are signals that the master device outputs to the slave device
when starting a serial transfer. The slave device includes hardware for detecting start conditions.
A start condition is output when bit 1 (STT) of the IIC control register (IICC) is set to 1 after a stop condition
has been detected (SPD: Bit 0 = 1 in IIC status register (IICS)). When a start condition is detected, bit 1 (STD)
of IICS is set to 1.
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CHAPTER 12 SERIAL INTERFACE FUNCTION
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C bus's serial data communication format and the signals used by the I
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Figure 12-25. I C Bus Serial Data Transfer Timing
1 to 7 8 9 1 to 7
R/W ACK Data
Figure 12-26. Start Conditions
H
SCL
SDA
Preliminary User's Manual U15905EJ1V0UD
8 9 1 to 7 8
ACK Data
2
C bus.
2
C bus's serial data bus is
9
ACK Stop
condition