Status Transition Diagram - NEC 78K0 User Manual

A status transition diagram of this product is shown in Figure 6-13, and the relationship between the operation
clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown
in Tables 6-3 and 6-4, respectively.
(1) When "Ring-OSC can be stopped by software" is selected by mask option
Status 4
RSTOP = 0
CPU clock: f
XP
f : Oscillating
XP
f : Oscillation stopped
R
RSTOP = 1
instruction
Notes 1. When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
(MCM) is 1.
2. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
3. When shifting from status 2 to status 1, make sure that MCS is 0.
4. When "Ring-OSC can be stopped by software" is selected by a mask option, the watchdog timer
stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog timer.
However, oscillation of Ring-OSC does not stop even in the HALT and STOP modes if RSTOP = 0.
5. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
156
CHAPTER 6 CLOCK GENERATOR
Figure 6-13. Status Transition Diagram (1/4)
(when subsystem clock is not used)
HALT
Interrupt
Interrupt
HALT HALT
instruction instruction
Status 3
MCM0 = 0
CPU clock: f
XP
f : Oscillating
XP
Note 1
f : Oscillating
MCM0 = 1
R
Interrupt
Interrupt
STOP
instruction
STOP
STOP
User's Manual U15947EJ2V0UD
Note 4
HALT instruction
HALT
Interrupt
instruction
Interrupt
Status 2
CPU clock: f
R
f : Oscillating
XP
Note 2
f : Oscillating
R
instruction
STOP
instruction
Interrupt
Note 4
*
Reset
Note 3 Status 1
MSTOP = 1
CPU clock: f
f : Oscillation stopped
XP
f : Oscillating
MSTOP = 0
R
STOP
Interrupt
Reset release
Note 5
R