Figure 8-3: Power Save Mode State Transition Diagram - NEC V850E/CA1 ATOMIC Preliminary User's Manual

32-/16-bit single-chip microcontroller
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Figure 8-3 shows the operation of the clock generator in normal operation mode, HALT mode, IDLE
mode, WATCH mode, and software STOP mode.
An effective low power consumption system can be realized by combining these modes and switching
modes according to the required use.

Figure 8-3: Power Save Mode State Transition Diagram

Watch mode
Release by RESET
NMI, or maskable interrupt
Release by RESET ,
NMI, or maskable interrupt
Software STOP mode
Notes:
1.
Switch off PLL if activated before.
2.
Enable PLL if required
The following table shows the supplied operating frequencies of all macros if a 4 MHz crystal is applied
to the oscillator circuit or an external clock signal with 16 MHz is applied to the CLOCKIN pin.
Chapter 8 Clock Generator
Set WATCH mode
,
Note 2
Normal operation mode
Note 2
Note 1
Set STOP mode
Preliminary User's Manual U14913EE1V0UM00
Note 1
Release by RESET ,
NMI, or maskable interrupt
Set HALT mode
Release by RESET ,
NMI, or maskable interrupt
Note 1
Set IDLE mode
IDLE mode
Note 2
HALT mode
Note 2
231

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