Voltage Regulator - ST STM32U5 Getting Started

When the backup domain is supplied by V
available:
• PC13, PC14, and PC15 that can be used as GPIO pins
• PC13, PC14, and PC15 that can be configured by RTC or LSE (refer to the RTC section of document [1])
• Pins listed below, that are configured by TAMP as tamper pins:
– PE3 (TAMP_IN6/TAMP_OUT3)
– PE4 (TAMP_IN7/TAMP_OUT8)
– PE5 (TAMP_IN8/TAMP_OUT7)
– PE6 (TAMP_IN3/TAMP_OUT6)
– PC13 (TAMP_IN1/TAMP_OUT2)
– PA0 (TAMP_IN2/TAMP_OUT1)
– PA1 (TAMP_IN5/TAMP_OUT4)
– PC5 (TAMP_IN4/TAMP_OUT5)
Note: • Because the power switch can transfer only a limited amount of current (3 mA), the use of PC13 to PC15
I/Os in output mode is restricted: the speed must be limited to 2 MHz with a maximum load of 30 pF.
These I/Os must not be used as current source (for example to drive an LED).
• Under V
the GPIOs to which they are connected. However, under V
limited to 500 kHz.
• The speed of the PC13 pin is always limited to 2 MHz, under V
Backup domain access
After a system reset, the backup domain (RCC_BDCR, PWR_BDCR1, RTC, TAMP and backup registers, plus
backup SRAM) is protected against possible unwanted write accesses. To enable access to the backup domain,
proceed as follows:
1. Enable the power interface clock by setting the PWREN bit RCC_AHB3ENR.
2. Set the DBP bit in PWR_DBPR to enable access to the backup domain.
V battery charging
BAT
When V is present, the external battery can be charged on V
DD
1.5 kΩ, depending on the VBRS bit in PWR_BDCR2.
The battery charging is enabled by setting VBE bit in PWR_BDCR2. It is automatically disabled in VBAT mode.
2.1.5

Voltage regulator

The STM32U5 devices embed the following internal regulators in parallel to provide the V
peripherals, SRAMs, and the embedded flash memory:
• SMPS step-down converter
• LDO (linear voltage regulator)
They can be selected when the application runs, depending on the application requirements. The SMPS allows
the power consumption to be reduced. However, the noise generated by the SMPS may impact some peripheral
behaviors, requiring the application to switch to LDO when running the peripheral, in order to reach the best
performances.
Except for Standby circuitries and the Backup domain, LDO or SMPS can be used in all voltage scaling ranges
(range 1/2/3/4), in all Stop modes (Stop 0/1/2/3), and in Standby mode with SRAM2. Refer to the low-power mode
summary table in document [1].
On some packages, the SMPS supply pins are not available, consequently only the LDO might be used to supply
V domain.
CORE
AN5373 - Rev 6
DD
, TAMP_OUTx pins (PE3, PE4, PE5, PE6, PA0, PA1, PC5) keep the same speed features as
DD
(analog switch connected to the VDD pin), the following pins are
, the speed of TAMP_OUTx pins must be
BAT
or under V
DD
through an internal resistance, 5 kΩ, or
BAT
AN5373
Power supplies
.
BAT
supply for digital
CORE
page 12/47