Motorola DSP56367 User Manual page 94

Specifications
External Memory Expansion Port (Port A)
Table 3-11 DRAM Page Mode Timings, Three Wait States (Continued)
No.
150 CAS assertion to data not valid (write)
151 WR assertion to CAS assertion
152 Last RD assertion to RAS deassertion
153 RD assertion to data valid
154
RD deassertion to data not valid
155 WR assertion to data active
156 WR deassertion to data high impedance
Note: 1. The number of wait states for Page mode access is specified in the DCR.
2. The refresh period is specified in the DCR.
3. The asynchronous delays specified in the expressions are valid for DSP56367.
4. All the timings are calculated for the worst case. Some of the timings are better for specific
cases (e.g., t
5. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be
inserted in each DRAM out-of page-access.
6. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
and not t
GZ
3-28
Characteristics
6
equals 4 × T
for read-after-read or write-after-write sequences).
PC C
.
DSP56367
Symbol Expression
2.5 × T − 4.0
t
DH C
1.25 × T − 4.3
t
WCS C
3.5 × T − 4.0
t
ROH C
2.5 × T − 7.0
t
GA C
t
GZ
0.75 × T − 0.3
C
0.25 × T
C
Ma
Min Unit
x
21.0 — ns
8.2 — ns
31.0 — ns
— 18.0 ns
0.0 — ns
7.2 — ns
— 2.5 ns
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