Motorola DSP56367 User Manual

24-bit digital signal processor.
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Revision 1.0
Published 02/01
DSP56367UM/D
(Motorola Order Number)
DSP56367
24-Bit Digital Signal Processor
User's Manual
Motorola, Incorporated
Semiconductor Products Sector
6501 William Cannon Drive West
Austin, TX 78735-8598

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   Summary of Contents for Motorola DSP56367

  • Page 1

    Revision 1.0 Published 02/01 DSP56367UM/D (Motorola Order Number) DSP56367 24-Bit Digital Signal Processor User’s Manual Motorola, Incorporated Semiconductor Products Sector 6501 William Cannon Drive West Austin, TX 78735-8598...

  • Page 2

    Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life.

  • Page 3: Table Of Contents

    1 DSP56367 Overview ........

  • Page 4: Table Of Contents

    Reserved Memory Spaces ........5-12 5.1.2 Program ROM Area Reserved for Motorola Use.....5-12 5.1.3 Bootstrap ROM .

  • Page 5: Table Of Contents

    Host Status Register (HSR)........8-10 MOTOROLA...

  • Page 6: Table Of Contents

    CVR Host Vector (HV[6:0]) Bits 0–6 ......8-25 8.6.2.2 CVR Host Command Bit (HC) Bit 7 ......8-25 MOTOROLA...

  • Page 7: Table Of Contents

    HCSR FIFO-Enable Control (HFIFO)—Bit 5 ....9-14 9.5.6.6 HCSR Master Mode (HMST)—Bit 6 ......9-14 MOTOROLA...

  • Page 8: Table Of Contents

    ESAI Programming Model.........10-9 viii MOTOROLA...

  • Page 9: Table Of Contents

    RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 2310-29 10.3.4 ESAI Receive Control Register (RCR)......10-30 MOTOROLA...

  • Page 10: Table Of Contents

    ESAI Transmit Shift Registers ........10-44 10.3.10 ESAI Transmit Data Registers (TX5, TX4, TX3, TX2,TX1,TX0) ..10-44 MOTOROLA...

  • Page 11: Table Of Contents

    ESAI_1 Transmit Control Register (TCR_1) ..... . 11-10 11.3.4 ESAI_1 Receive Clock Control Register (RCCR_1) ....11-10 MOTOROLA...

  • Page 12: Table Of Contents

    Block Transferred Interrupt Enable (XBIE)—Bit 2 ....12-8 12.5.6.4 DAX Clock Input Select (XCS[1:0])—Bits 3–4 ....12-8 MOTOROLA...

  • Page 13: Table Of Contents

    TCSR Inverter (INV) Bit 8 ........13-9 MOTOROLA...

  • Page 14: Table Of Contents

    DSP56367 Bootstrap Program ........

  • Page 15: Table Of Contents

    Index ..............1 MOTOROLA...

  • Page 16

    CONTENTS Paragraph Page Title Number Number MOTOROLA...

  • Page 17

    DSP56367 Block Diagram ........1-2...

  • Page 18

    Interface Status Register (ISR) ........8-26 xviii MOTOROLA...

  • Page 19

    TCCR_1 Register ..........11-7 MOTOROLA...

  • Page 20

    14-2 DSP56367 144-pin LQFP Package.......14-7 Status Register (SR) ..........D-16 Operating Mode Register (OMR) .

  • Page 21

    GPIO Port E ........... . . D-51 MOTOROLA...

  • Page 22

    List of Figures Figure Page Title Number Number xxii MOTOROLA...

  • Page 23

    Number DSP56367 Functional Signal Groupings ......2-1 Power Inputs ..........2-4 Grounds.

  • Page 24

    Operating Mode Register (OMR) ....... .6-2 DSP56367 Operating Modes ........6-5 DSP56367 Mode Descriptions .

  • Page 25

    Internal I/O Memory Map........D-2 DSP56367 Interrupt Vectors........D-7 Interrupt Sources Priorities Within an IPL .

  • Page 26

    List of Tables Table Page Title Number Number xxvi MOTOROLA...

  • Page 27

    This document, as well as Motorola’s DSP development tools, can be obtained through a local Motorola Semiconductor Sales Office or authorized distributor. To receive the latest information on this DSP, access the Motorola DSP home page at the address given on the front cover of this document.

  • Page 28

    Explains the operating modes and how they affect the processor’s program and data memories. SECTION 7—GENERAL PURPOSE INPUT/OUTPUT (GPIO) – Describes the DSP56367 GPIO capability and the programming model for the GPIO signals (operation, registers, and control). SECTION 8— HOST INTERFACE (HDI08) –...

  • Page 29: Manual Conventions

    – Provides the BSDL listing for the DSP56367. APPENDIX D—PROGRAMMING REFERENCE – Lists peripheral addresses, interrupt addresses, and interrupt priorities for the DSP56367. Contains programming sheets listing the contents of the major DSP56367 registers for programmer reference. APPENDIX E—POWER CONSUMPTION BENCHMARK –...

  • Page 30

    The word “reset” is used in four different contexts in this manual: – the reset signal, written as “RESET,” – the reset instruction, written as “RESET,” – the reset operating state, written as “Reset,” and – the reset function, written as “reset.” About This Guide MOTOROLA...

  • Page 31: Section 1 Dsp56367 Overview

    (MIPS) using an internal 150 MHz clock at 1.8 V and 100 million instructions per second (MIPS) using an internal 100 MHz clock at 1.5 V. Changes in core functionality specific to the DSP56367 are also described in this manual. See Figure 1-1 for the block diagram of the DSP56367.

  • Page 32: Dsp56300 Core Description

    Figure 1-1 DSP56367 Block Diagram DSP56300 CORE DESCRIPTION The DSP56367 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides up to twice the performance of Motorola’s popular DSP56000 core family while retaining code compatibility with it.

  • Page 33

    DSP56367 Overview DSP56300 Core Description core, see Section 1 DSP56300 Core Functional Blocks on page 1-5. Significant architectural enhancements to the DSP56300 core family include a barrel shifter, 24-bit addressing, an instruction cache, and direct memory access (DMA). The DSP56300 core family members contain the DSP56300 core and additional modules. The modules are chosen from a library of standard predesigned elements such as memories and peripherals.

  • Page 34: Dsp56367 Audio Processor Architecture

    • 144-pin plastic LQFP package. DSP56367 AUDIO PROCESSOR ARCHITECTURE This section defines the DSP56367 audio processor architecture. The audio processor is composed of the following units: • The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program...

  • Page 35: Dsp56300 Core Functional Blocks

    • JTAG TAP • Memory In addition, the DSP56367 provides a set of on-chip peripherals, described in Section 1 Peripheral Overview on page 1-11. 1.4.1 DATA ALU The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core.

  • Page 36: Data Alu Registers

    DSP56367 Overview DSP56300 Core Functional Blocks • Conditional ALU instructions • 24-bit or 16-bit arithmetic support under software control • Four 24-bit input general purpose registers: X1, X0, Y1, and Y0 • Six Data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two general purpose, 56-bit accumulators (A and B), accumulator shifters •...

  • Page 37: Program Control Unit (pcu)

    DSP56367 Overview DSP56300 Core Functional Blocks The AGU is divided into two halves, each with its own Address ALU. Each Address ALU has four sets of register triplets, and each register triplet is composed of an address register, an offset register, and a modifier register. The two Address ALUs are identical. Each contains a 24-bit full adder (called an offset adder).

  • Page 38: Internal Buses

    DSP56367 Overview DSP56300 Core Functional Blocks • On-chip memory-expandable hardware stack • Nested hardware DO loops • Fast auto-return interrupts The PCU implements its functions using the following registers: • PC—program counter register • SR—Status register • LA—loop address register •...

  • Page 39: Direct Memory Access (dma)

    DSP56367 Overview DSP56300 Core Functional Blocks • Program address bus (PAB) for carrying program memory addresses throughout the core • X memory address bus (XAB) for carrying X memory addresses throughout the core • Y memory address bus (YAB) for carrying Y memory addresses throughout the core All internal buses on the DSP56300 family members are 24-bit buses.

  • Page 40: Jtag Tap And Once Module

    DSP56367 Overview DSP56300 Core Functional Blocks 1.4.7 JTAG TAP AND ONCE MODULE The DSP56300 core provides a dedicated user-accessible TAP fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards led to developing this standard under the sponsorship of the Test Technology Committee of IEEE and JTAG.

  • Page 41: Off-chip Memory Expansion

    On-chip dynamic RAM (DRAM) controller for glueless interface to DRAM • Eighteen external address lines PERIPHERAL OVERVIEW The DSP56367 is designed to perform a wide variety of fixed-point digital signal processing functions. In addition to the core features previously discussed, the DSP56367 provides the following peripherals: •...

  • Page 42: Host Interface (hdi08)

    DSP56367 Overview Peripheral Overview 1.5.1 HOST INTERFACE (HDI08) The host interface (HDI08) is a byte-wide, full-duplex, double-buffered, parallel port that can be connected directly to the data bus of a host processor. The HDI08 supports a variety of buses and provides glueless connection with a number of industry-standard DSPs, microcomputers, microprocessors, and DMA hardware.

  • Page 43: Triple Timer (tec)

    The ESAI provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Motorola SPI serial protocol. The ESAI consists of independent transmitter and receiver sections, each with its own clock generator. It is a superset of the DSP56300 family ESSI peripheral and of the DSP56000 family SAI peripheral.

  • Page 44: Serial Host Interface (shi)

    DSP and an external host processor. The SHI can also communicate with other serial peripheral devices. The SHI can interface directly to either of two well-known and widely used synchronous serial buses: the Motorola serial peripheral interface (SPI) bus and the Philips inter-integrated-circuit control (I C) bus.

  • Page 45: Section 2 Signal/connection Descriptions

    SIGNAL/CONNECTION DESCRIPTIONS SIGNAL GROUPINGS The input and output signals of the DSP56367 are organized into functional groups, which are listed in Table 2-1 and illustrated in Figure 2-1. The DSP56367 is operated from a 1.8V supply; however, some of the inputs can tolerate 3.3V.

  • Page 46

    Signal/Connection Descriptions Signal Groupings Table 2-1 DSP56367 Functional Signal Groupings (Continued) Number of Detailed Functional Group Signals Description JTAG/OnCE Port Table 2-15 Note: Port A is the external memory interface port, including the external address bus, data bus, and control signals.

  • Page 47

    Signal/Connection Descriptions Signal Groupings OnCE™ ON-CHIP EMULATION/ PORT A ADDRESS BUS JTAG PORT DSP56367 A0-A17 VCCA (3) GNDA (4) PORT A DATA BUS PARALLEL HOST PORT (HDI08) D0-D23 HAD(7:0) [PB0-PB7] Port B VCCD (4) HAS/HA0 [PB8] GNDD (4) HA8/HA1 [PB9]...

  • Page 48: Power

    There is one GND connection. Quiet Ground—GND is an isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GND connections. DSP56367 MOTOROLA...

  • Page 49: Clock And Pll

    PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET de assertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized to internal system clock. MOTOROLA DSP56367...

  • Page 50: External Memory Expansion Port (port A)

    External Memory Expansion Port (Port A) EXTERNAL MEMORY EXPANSION PORT (PORT A) When the DSP56367 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0–AA2/RAS2, RD, WR, BB, CAS.

  • Page 51

    BR is deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independent of whether the DSP56367 is a bus master or a bus slave. Bus “parking” allows BR to be deasserted even though the DSP56367 is the bus master.

  • Page 52: Interrupt And Mode Control

    MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. This input is 3.3V tolerant. DSP56367 MOTOROLA...

  • Page 53: Parallel Host Interface (hdi08)

    The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The HDI08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware. MOTOROLA DSP56367...

  • Page 54

    Port B 9—When the HDI08 is configured as GPIO, this signal is disconnected individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant. 2-10 DSP56367 MOTOROLA...

  • Page 55

    Port B 12—When the HDI08 is configured as GPIO, this signal is disconnected individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant. MOTOROLA DSP56367 2-11...

  • Page 56

    Port B 15—When the HDI08 is configured as GPIO, this signal is disconnected individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant. 2-12 DSP56367 MOTOROLA...

  • Page 57: Serial Host Interface

    SDA while SCL is high is a unique situation defined as the stop event. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 3.3V tolerant. MOTOROLA DSP56367 2-13...

  • Page 58

    This signal is tri-stated during hardware, software, personal reset, or when the HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in this state. This input is 3.3V tolerant. 2-14 DSP56367 MOTOROLA...

  • Page 59: Enhanced Serial Audio Interface

    Input, output, or Port C 1—When the ESAI is configured as GPIO, this signal is individually disconnected programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. MOTOROLA DSP56367 2-15...

  • Page 60

    Input, output, or Port C 6—When the ESAI is configured as GPIO, this signal is individually disconnected programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. 2-16 DSP56367 MOTOROLA...

  • Page 61

    Port C 10—When the ESAI is configured as GPIO, this signal is individually disconnected programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 10 signal. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. MOTOROLA DSP56367 2-17...

  • Page 62

    Port C 11—When the ESAI is configured as GPIO, this signal is individually disconnected programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 11 signal. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. 2-18 DSP56367 MOTOROLA...

  • Page 63: Enhanced Serial Audio Interface_1

    Input, output, or Port E 0—When the ESAI is configured as GPIO, this signal is individually disconnected programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 3.3V. MOTOROLA DSP56367 2-19...

  • Page 64: Spdif Transmitter Digital Audio Interface

    Input, Port D 0—When the DAX is configured as GPIO, this signal is individually output, or programmable as input, output, or internally disconnected. disconnected The default state after reset is GPIO disconnected. This input is 3.3V tolerant. 2-20 DSP56367 MOTOROLA...

  • Page 65: Timer

    State Signal Signal during Signal Description Name Type Reset Input Input Test Clock—TCK is a test clock input signal used to synchronize the JTAG test logic. It has an internal pull-up resistor. This input is 3.3V tolerant. MOTOROLA DSP56367 2-21...

  • Page 66

    Input Input Test Mode Select—TMS is an input signal used to sequence the test controller’s state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 3.3V tolerant. 2-22 DSP56367 MOTOROLA...

  • Page 67: Section 3 Specifications

    SECTION SPECIFICATIONS INTRODUCTION The DSP56367 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs and outputs. Note: This document contains information on a new product. Specifications and information herein are subject to change without notice. Finalized specifications may be published after further characterization and device qualifications are completed.

  • Page 68: Thermal Characteristics

    Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. THERMAL CHARACTERISTICS Table 3-2 Thermal Characteristics Characteristic Symbol TQFP Value Unit or θ 49.87 ° θJA Junction-to-ambient thermal resistance or θ 9.26 ° θJC Junction-to-case thermal resistance Ψ Thermal characterization parameter ° DSP56367 MOTOROLA...

  • Page 69

    Measurements were done with parts mounted on thermal test boards conforming to specification EIA/JESD51-3. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that the cold plate temperature is used for the case temperature. MOTOROLA DSP56367...

  • Page 70: Dc Electrical Characteristics

    Output high voltage — — Output low voltage — — Internal supply current at internal clock of 150MHz — 58.0 In Normal mode In Wait mode — — In Stop mode PLL supply current — — — Input capacitance DSP56367 MOTOROLA...

  • Page 71: Ac Electrical Characteristics

    2.4 V for all pins except EXTAL. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal’s transition. DSP56367 output levels are measured with the production test machine V and V reference levels set at 0.4 V and...

  • Page 72: Internal Clocks

    Note: DF = Division Factor Ef = External frequency = External clock cycle MF = Multiplication Factor PDF = Predivision Factor = internal clock cycle DSP56300 Family Manual Refer to the for a detailed discussion of the PLL. DSP56367 MOTOROLA...

  • Page 73: External Clock Operation

    Specifications External Clock Operation EXTERNAL CLOCK OPERATION The DSP56367 system clock is an externally supplied square wave voltage source connected to EXTAL(Figure 3-1). Midpoint EXTAL Note: The midpoint is 0.5 (V Figure 3-1 E xternal Clock Timing Table 3-5 Clock Operation...

  • Page 74: Phase Lock Loop (pll) Characteristics

    PLL capacitor (connected between the PCAP pin and V ). The PCAP recommended value in pF for C can be computed from one of the following equations: PCAP (MF x 680)-120, for MF ≤ 4, or MF x 1100, for MF > 4. DSP56367 MOTOROLA...

  • Page 75: Reset, Stop, Mode Select, And Interrupt Timing

    Note 7 instruction execute to interrupt request deassertion for level sensitive fast interrupts 3.25 × T + WS × T Delay from RD assertion to interrupt request deassertion for – 10.94 — Note 7 level sensitive fast interrupts MOTOROLA DSP56367...

  • Page 76

    × T (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) 5.5 × T • PLL is active during Stop (PCTL 45.8 — Bit 17 = 1) (implies no Stop delay) 3-10 DSP56367 MOTOROLA...

  • Page 77

    — 100.0 DMA Requests Rate • Data read from HDI08, ESAI, — 50.0 ESAI_1, SHI, DAX • Data write to HDI08, ESAI, — 58.0 ESAI_1, SHI, DAX • Timer 16.7 • IRQ, NMI (edge trigger) — 25.0 MOTOROLA DSP56367 3-11...

  • Page 78

    If PLL does not lose lock = 1.8 V ± 5%; T = 0°C to + 95°C, C = 50 pF WS = number of wait states (measured in clock cycles, number of T ). Use expression to compute maximum value. 3-12 DSP56367 MOTOROLA...

  • Page 79

    Specifications Reset, Stop, Mode Select, and Interrupt Timing RESET All Pins Reset Value A0–A17 First Fetch AA0460 Figure 3-2 Reset Timing MOTOROLA DSP56367 3-13...

  • Page 80

    Reset, Stop, Mode Select, and Interrupt Timing First Interrupt Instruction A0–A17 Execution/Fetch IRQA, IRQB, IRQC, IRQD, a) First Interrupt Instruction Execution General Purpose IRQA, IRQB, IRQC, IRQD, b) General Purpose I/O Figure 3-3 External Fast Interrupt Timing 3-14 DSP56367 MOTOROLA...

  • Page 81

    Figure 3-4 External Interrupt Timing (Negative Edge-Triggered) RESET IRQA, IRQB, MODA, MODB, IRQD, NMI MODC, MODD, PINIT AA0465 Figure 3-5 Operating Mode Select Timing IRQA First Instruction Fetch A0–A17 AA0466 Figure 3-6 Recovery from Stop State Using IRQA Interrupt Service MOTOROLA DSP56367 3-15...

  • Page 82

    First IRQA Interrupt A0–A17 Instruction Fetch AA0467 Figure 3-7 Recovery from Stop State Using IRQA Interrupt Service DMA Source Address A0–A17 IRQA, IRQB, First Interrupt Instruction Execution IRQC, IRQD, AA110 Figure 3-8 External Memory Access (DMA Source) Timing 3-16 DSP56367 MOTOROLA...

  • Page 83

    [WS ≥ 8] All frequencies: 12.0 — 1.75 × T 2.25 × T 14.7 — [WS ≥ 8] (WS + 0.75) × T − 7.0 Address and AA valid to input data valid — [WS ≥ 1] MOTOROLA DSP56367 3-17...

  • Page 84

    − 4.0 Previous RD deassertion to data active (write) — — [1 ≤ WS ≤ 3] 2.25 × T − 4.0 14.7 — [4 ≤ WS ≤ 7] 3.25 × T − 4.0 23.1 — [WS ≥ 8] 3-18 DSP56367 MOTOROLA...

  • Page 85

    · · All timings for 100 MHz are measured from 0.5 Vcc to .05 In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active MOTOROLA DSP56367 3-19...

  • Page 86

    Specifications External Memory Expansion Port (Port A) A0–A17 AA0–AA2 Data D0–D23 AA0468 Figure 3-9 SRAM Read Access 3-20 DSP56367 MOTOROLA...

  • Page 87

    Specifications External Memory Expansion Port (Port A) A0–A17 AA0–AA2 Data D0–D23 Figure 3-10 SRAM Write Access MOTOROLA DSP56367 3-21...

  • Page 88: Dram Timing

    This figure should be use for primary selection. DRAM Type For exact and detailed timings see the following tables. Chip Frequency (MHz) 1 Wait States 3 Wait States 2 Wait States 4 Wait States AA047 Figure 3-11 DRAM Page Mode Wait States Selection Guide 3-22 DSP56367 MOTOROLA...

  • Page 89

    0.25 × T − 3.7 CAS deassertion to WR assertion — — 0.5 × T − 4.2 CAS assertion to WR deassertion 20.8 — 12.5 — 1.5 × T − 4.5 70.5 — 45.5 — WR assertion pulse widt MOTOROLA DSP56367 3-23...

  • Page 90

    Unit 2 × T Page mode cycle time for two 45.4 — 37.5 — consecutive accesses of the same direction 1.25 × T Page mode cycle time for 41.1 — 34.4 — mixed (read and write) accesses 3-24 DSP56367 MOTOROLA...

  • Page 91

    Last column address valid to 41.5 — 33.5 — RAS deassertion 1.25 × T − 3.8 WR deassertion to CAS 15.1 — 11.8 — assertion 0.5 × T − 3.7 CAS deassertion to WR — — assertion MOTOROLA DSP56367 3-25...

  • Page 92

    The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56367. All the timings are calculated for the worst case. Some of the timings are better for specific equals 3 ×...

  • Page 93

    3.75 × T − 4.3 Last WR assertion to RAS deassertion 33.2 — 3.25 × T − 4.3 WR assertion to CAS deassertion 28.2 — 0.5 × T − 4.0 Data valid to CAS assertion (write) — MOTOROLA DSP56367 3-27...

  • Page 94

    The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56367. All the timings are calculated for the worst case. Some of the timings are better for specific equals 4 ×...

  • Page 95

    0.5 × T − 4.0 Data valid to CAS assertion (write) — 3.5 × T − 4.0 CAS assertion to data not valid (write) 25.2 — 1.25 × T − 4.3 WR assertion to CAS assertion — MOTOROLA DSP56367 3-29...

  • Page 96

    The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. DSP56367 The asynchronous delays specified in the expressions are valid for All the timings are calculated for the worst case. Some of the timings are better for specific equals 3 ×...

  • Page 97

    Specifications External Memory Expansion Port (Port A) Column Last Column Column A0–A17 Address Address Address D0–D23 Data Out Data Out Data Out AA0473 Figure 3-12 DRAM Page Mode Write Accesses MOTOROLA DSP56367 3-31...

  • Page 98

    Specifications External Memory Expansion Port (Port A) Column Column Last Column A0–A17 Address Address Address D0–D23 Data In Data In Data In AA0474 Figure 3-13 DRAM Page Mode Read Accesses 3-32 DSP56367 MOTOROLA...

  • Page 99

    − 7.5 Column address valid to data valid — 67.5 — 42.5 (read) CAS deassertion to data not valid (read — — hold time) 1.75 × T − 4.0 RAS deassertion to RAS assertion 83.5 — 54.3 — MOTOROLA DSP56367 3-33...

  • Page 100

    Data valid to CAS assertion (write) 108.5 — 71.0 — 1.75 × T − 4.0 CAS assertion to data not valid (write) 83.5 — 54.3 — 3.25 × T − 4.0 RAS assertion to data not valid (write) 158.5 — 104.3 — 3-34 DSP56367 MOTOROLA...

  • Page 101

    26.6 — — 2.25 × T − 6.5 — — — 21.6 3 × T − 7.5 Column address valid to data valid — 40.0 — — (read) 3 × T − 6.5 — — — 31.0 MOTOROLA DSP56367 3-35...

  • Page 102

    0.25 × T − 3.0 — — — 3 × T − 4.2 CAS assertion to WR deassertion 41.3 — 33.3 — 5.5 × T − 4.2 RAS assertion to WR deassertion 79.1 — 64.6 — 3-36 DSP56367 MOTOROLA...

  • Page 103

    The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56367. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t...

  • Page 104

    RAS deassertion to WR assertion 5 × T − 4.2 CAS assertion to WR deassertion 45.8 — 7.5 × T − 4.2 RAS assertion to WR deassertion 70.8 — 11.5 × T − 4.5 WR assertion pulse width 110.5 — 3-38 DSP56367 MOTOROLA...

  • Page 105

    The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56367. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t...

  • Page 106

    15.75 × T − 4.3 WR assertion to RAS deassertion 126.9 — 14.25 × T − 4.3 WR assertion to CAS deassertion 114.4 — 8.75 × T − 4.0 Data valid to CAS assertion (write) 68.9 — 3-40 DSP56367 MOTOROLA...

  • Page 107

    The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is and not t Either t or t must be satisfied for read cycles. MOTOROLA DSP56367 3-41...

  • Page 108

    Specifications External Memory Expansion Port (Port A) A0–A17 Row Address Column Address Data D0–D23 AA0476 Figure 3-15 DRAM Out-of-Page Read Access 3-42 DSP56367 MOTOROLA...

  • Page 109

    Specifications External Memory Expansion Port (Port A) Row Address Column Address A0–A17 Data Out D0–D23 AA0477 Figure 3-16 DRAM Out-of-Page Write Access MOTOROLA DSP56367 3-43...

  • Page 110

    Specifications External Memory Expansion Port (Port A) AA0478 Figure 3-17 DRAM Refresh Access 3-44 DSP56367 MOTOROLA...

  • Page 111: Arbitration Timings

    In order to guarantee timings 250, and 251, it is recommended to assert BG inputs to different 56300 devices (on the same bus) in a non overlap manner as shown in Figure 3-18. Figure 3-18 Asynchronous Bus Arbitration Timing MOTOROLA DSP56367 3-45...

  • Page 112: Parallel Host Interface (hdi08) Timing

    PARALLEL HOST INTERFACE (HDI08) TIMING Table 3-18 Host Interface (HDI08) Timing 120 MHz Expression Unit Characteristics + 9.9 18.3 — Read data strobe assertion width HACK read assertion width — — Read data strobe deassertion width HACK read deassertion width 3-46 DSP56367 MOTOROLA...

  • Page 113

    Output data hold time after read data strobe deassertion Output data hold time after HACK read deassertion +9.9 18.2 — HCS assertion to read data strobe deassertion — — HCS assertion to write data strobe deassertion HCS assertion to output data valid — — 19.1 MOTOROLA DSP56367 3-47...

  • Page 114

    Delay from DMA HACK assertion to HOREQ deassertion — — 20.2 HROD = 0 5 • Delay from DMA HACK assertion to HOREQ deassertion for — — 300.0 “Last Data Register” read or write HROD = 1, open drain Host Request 5, 11 • 3-48 DSP56367 MOTOROLA...

  • Page 115

    Expression Unit Characteristics Note: See Host Port Usage Considerations in the DSP56367 User’s Manual. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. = 1.8 V ± 5%; T = 0°C to +95°C, C...

  • Page 116

    Specifications Parallel Host Interface (HDI08) Timing HA0–HA2 HRD, HDS HD0–HD7 HOREQ, HRRQ, HTRQ AA0484 Figure 3-21 Read Timing Diagram, Non-Multiplexed Bus 3-50 DSP56367 MOTOROLA...

  • Page 117

    Specifications Parallel Host Interface (HDI08) Timing HA0–HA2 HWR, HDS HD0–HD7 HOREQ, HRRQ, HTRQ AA0485 Figure 3-22 Write Timing Diagram, Non-Multiplexed Bus MOTOROLA DSP56367 3-51...

  • Page 118

    Specifications Parallel Host Interface (HDI08) Timing HA8–HA10 HRD, HDS HAD0–HAD7 Address Data HOREQ, HRRQ, HTRQ AA0486 Figure 3-23 Read Timing Diagram, Multiplexed Bus 3-52 DSP56367 MOTOROLA...

  • Page 119

    Specifications Parallel Host Interface (HDI08) Timing HA8–HA10 HWR, HDS HAD0–HAD7 Data Address HOREQ, HRRQ, HTRQ AA0487 Figure 3-24 Write Timing Diagram, Multiplexed Bus MOTOROLA DSP56367 3-53...

  • Page 120

    Parallel Host Interface (HDI08) Timing HOREQ (Output) TXH/M/L HACK Write (Input) Data H0–H7 Valid (Input) Figure 3-25 Host DMA Write Timing Diagram HOREQ (Output) HACK (Input) Read H0-H7 Data (Output) Valid Figure 3-26 Host DMA Read Timing Diagram 3-54 DSP56367 MOTOROLA...

  • Page 121: Serial Host Interface Spi Protocol Timing

    –10 — SPICC Wide 0.5×t –10 126.5 — SPICC Slave Bypassed 2.5×T 32.8 — Narrow 2.5×T +102 122.8 — Wide 2.5×T +189 209.8 — Serial clock rise/fall time Maste — — — Slave — — — 2000 MOTOROLA DSP56367 3-55...

  • Page 122

    226.7 SCK edge to data out not valid Maste Bypassed 13.3 — (data out hold time) r/Slav Narrow 63.3 — Wide +106 114.3 — SS assertion to data out valid Slave — — 41.3 (CPHA = 0) 3-56 DSP56367 MOTOROLA...

  • Page 123

    (HREQ in set-up time) (CPHA = 1) First SCK edge to HREQ in not asserted Maste — — (HREQ in hold time) = 1.8 V ± 5%; T Note: = 0°C to +95°C, C = 50 pF Periodically sampled, not 100% tested MOTOROLA DSP56367 3-57...

  • Page 124

    Specifications Serial Host Interface SPI Protocol Timing (Input) SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) MISO (Input) Valid Valid MOSI (Output) HREQ (Input) AA027 Figure 3-27 SPI Master Timing (CPHA = 0) 3-58 DSP56367 MOTOROLA...

  • Page 125

    Specifications Serial Host Interface SPI Protocol Timing (Input) SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) MISO (Input) Valid Valid MOSI (Output) HREQ (Input) AA0272 Figure 3-28 SPI Master Timing (CPHA = 1) MOTOROLA DSP56367 3-59...

  • Page 126

    Specifications Serial Host Interface SPI Protocol Timing (Input) SCK (CPOL = 0) (Input) SCK (CPOL = 1) (Input) MISO (Output) MOSI (Input) Valid Valid HREQ (Output) AA027 Figure 3-29 SPI Slave Timing (CPHA = 0) 3-60 DSP56367 MOTOROLA...

  • Page 127

    Specifications Serial Host Interface SPI Protocol Timing (Input) SCK (CPOL = 0) (Input) SCK (CPOL = 1) (Input) MISO (Output) MOSI (Input) Valid Valid HREQ (Output) AA027 Figure 3-30 SPI Slave Timing (CPHA = 1) MOTOROLA DSP56367 3-61...

  • Page 128

    First SCL sampling edge to HREQ output NG;RQO deassertion × Filters bypassed — 46.7 — 46.7 + 30 × Narrow filters enabled — 136.7 — 136.7 + 120 × Wide filters enabled — 224.7 — 224.7 + 208 3-62 DSP56367 MOTOROLA...

  • Page 129: Programming The Serial Clock

    – HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be selected. In I C mode, the user may select a value for the programmed serial clock cycle from MOTOROLA DSP56367 3-63...

  • Page 130

    × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)] = [T = [8.33ns × 2 × (65 + 1) × (7 × (1 – 0) + 1)] = [8.33ns × 2 × 66 × 8] = 8796.48ns 3-64 DSP56367 MOTOROLA...

  • Page 131

    Specifications Serial Host Interface (SHI) I C Protocol Timing Stop Stop Start HREQ AA027 Figure 3-31 I C Timing MOTOROLA DSP56367 3-65...

  • Page 132: Enhanced Serial Audio Interface Timing

    FSR input (wl) high before RXC falling edge — — 23.0 — x ck — i ck a FSR input hold time after RXC falling edge — — — x ck — i ck a 3-66 DSP56367 MOTOROLA...

  • Page 133

    31.0 — assertion FST input (wl) setup time before TXC falling — — — x ck edge 21.0 — i ck FST input hold time after TXC falling edge — — — x ck — i ck MOTOROLA DSP56367 3-67...

  • Page 134

    (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. Periodically sampled and not 100% tested 3-68 DSP56367 MOTOROLA...

  • Page 135

    In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. AA0490 Figure 3-32 ESAI Transmitter Timing MOTOROLA DSP56367 3-69...

  • Page 136

    Specifications Enhanced Serial Audio Interface Timing (Input/Output) FSR (Bit) FSR (Word) Data In Last Bit First Bit FSR (Bit) FSR (Word) Flags In AA0491 Figure 3-33 ESAI Receiver Timing 3-70 DSP56367 MOTOROLA...

  • Page 137

    Specifications Enhanced Serial Audio Interface Timing HCKT SCKT(output) Figure 3-34 ESAI HCKT Timing HCKR SCKR (output) Figure 3-35 ESAI HCKR Timing MOTOROLA DSP56367 3-71...

  • Page 138: Digital Audio Transmitter Timing

    In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56367 internal clock frequency. For example, if the DSP56367 is running at 150 MHz internally, the ACI frequency should be less than 75 MHz.

  • Page 139: Timer Timing

    2 × T + 2.0 18.7 — TIO High 2 × T + 2.0 18.7 — 1.8 V ± 0.09 Note: V; T = 0°C to +95°C, C = 50 pF AA0492 Figure 3-37 TIO Timer Event Input Restrictions MOTOROLA DSP56367 3-73...

  • Page 140: Gpio Timing

    Valid only when PLL enabled with multiplication factor equal to one. EXTAL (Input) GPIO (Output) GPIO Valid (Input) A0–A17 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register. GPIO (Output) 3-74 DSP56367 MOTOROLA...

  • Page 141: Jtag Timing

    = 1.8 V ± 0.09 V; T Note: = 0°C to +95°C, C = 50 pF All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. (Input) AA0496 Figure 3-39 Test Clock Input Timing Diagram MOTOROLA DSP56367 3-75...

  • Page 142

    Data Outputs Data Output Data Valid Outputs AA0497 Figure 3-40 Boundary Scan (JTAG) Timing Diagram (Input) Input Data Valid (Input) Output Data Valid (Output) (Output) Output Data Valid (Output) AA0498 Figure 3-41 Test Access Port Timing Diagram 3-76 DSP56367 MOTOROLA...

  • Page 143: Section 4 Design Considerations

    The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from R do not θJA satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. MOTOROLA DSP56367...

  • Page 144

    The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. DSP56367 MOTOROLA...

  • Page 145: Electrical Design Considerations

    Take special care to minimize noise levels on the V and GND pins. • If multiple DSP56367 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. MOTOROLA DSP56367...

  • Page 146: Power Consumption Considerations

    For applications that require very low current consumption, do the following: • Set the EBD bit when not accessing external memory. • Minimize external memory accesses and use internal memory accesses. • Minimize the number of pins that are switching. DSP56367 MOTOROLA...

  • Page 147: Pll Performance Issues

    (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be 2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values. MOTOROLA DSP56367...

  • Page 148

    Design Considerations PLL Performance Issues DSP56367 MOTOROLA...

  • Page 149: Section 5 Memory Configuration

    MEMORY CONFIGURATION DATA AND PROGRAM MEMORY MAPS The on-chip memory configuration of the DSP56367 is affected by the state of the CE (Cache Enable), MSW0, MSW1, and MS (Memory Switch) control bits in the OMR register, and by the SC bit in the Status Register. The internal data and program memory configurations are shown in Table 5-1.

  • Page 150

    Cache $0000 - $0BFF n.a. $0000 - $33FF $0000-$1BFF $0000 - $07FF enabled $0000 - $33FF $0000-$1BFF $0000 -$27FF n.a. $0000 - $1FFF $0000 - $13FF $0000 - $1BFF and n.a. $0000 - $1FFF $0000-$1BFF $2400 - $27FF DSP56367 MOTOROLA...

  • Page 151

    $0000 - $1BFF Table 5-3 On-chip ROM Memory Locations Bit Settings ROM Memory Locations Prog. Boot. X Data Y Data MSW1 MSW0 $FF1000 - $FF0000 - $004000- $004000- $FFAFFF $FF00BF $00BFFF $005FFF no access no access $004000- $004000- $00BFFF $005FFF MOTOROLA DSP56367...

  • Page 152

    EXTERNAL $00C000 $006000 32K INTERNAL 8K INTERNAL $004000 EXTERNAL $004000 INT. RESERVED INT. RESERVED $003400 $001C00 $000800 13K INTERNAL 7K INTERNAL 2K INTERNAL $000000 $000000 $000000 1K I-CACHE ENABLED Figure 5-2 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=0 DSP56367 MOTOROLA...

  • Page 153

    32K INTERNAL 8K INTERNAL EXTERNAL $004000 $004000 INT. RESERVED INT. RESERVED $002800 $002000 $001C00 1K RAM $002400 INT. RESERVED $001C00 8K INTERNAL 7K INTERNAL 7K INTERNAL $000000 $000000 $000000 Figure 5-4 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=0 MOTOROLA DSP56367...

  • Page 154

    EXTERNAL $00C000 $006000 32K INTERNAL 8K INTERNAL $004000 $004000 EXTERNAL INT. RESERVED INT. RESERVED $002000 $001400 $002400 8K INTERNAL 5K INTERNAL 9K INTERNAL $000000 $000000 $000000 1K I-CACHE ENABLED Figure 5-6 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=0 DSP56367 MOTOROLA...

  • Page 155

    32K INTERNAL 8K INTERNAL $004000 $004000 EXTERNAL INT. RESERVED INT. RESERVED $002C00 $001C00 $002400 INT. RESERVED $001000 11K INTERNAL 7K INTERNAL 4K INTERNAL $000000 $000000 $000000 1K I-CACHE ENABLED Figure 5-8 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=0 MOTOROLA DSP56367...

  • Page 156

    EXTERNAL EXTERNAL $C000 $6000 32K INTERNAL 8K INTERNAL $4000 $4000 INT. RESERVED INT. RESERVED $3400 $1C00 $0800 13K INTERNAL 7K INTERNAL 2K INTERNAL $0000 $0000 $0000 1K I-CACHE ENABLED Figure 5-10 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=1 DSP56367 MOTOROLA...

  • Page 157

    $6000 32K INTERNAL 8K INTERNAL $4000 $4000 INT. RESERVED INT. RESERVED $2800 $2000 $1C00 1K RAM $2400 INT. RESERVED $1C00 8K INTERNAL 7K INTERNAL 7K INTERNAL $0000 $0000 $0000 Figure 5-12 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=1 MOTOROLA DSP56367...

  • Page 158

    EXTERNAL $C000 $6000 32K INTERNAL 8K INTERNAL $4000 $4000 INT. RESERVED INT. RESERVED $2000 $1400 $2400 8K INTERNAL 5K INTERNAL 9K INTERNAL $0000 $0000 $0000 1K I-CACHE ENABLED Figure 5-14 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=1 5-10 DSP56367 MOTOROLA...

  • Page 159

    32K INTERNAL 8K INTERNAL $4000 $4000 INT. RESERVED INT. RESERVED $2C00 $1C00 $2400 INT. RESERVED $1000 11K INTERNAL 7K INTERNAL 4K INTERNAL $0000 $0000 $0000 1K I-CACHE ENABLED Figure 5-16 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=1 MOTOROLA DSP56367 5-11...

  • Page 160: Reserved Memory Spaces

    5.1.2 PROGRAM ROM AREA RESERVED FOR MOTOROLA USE The last 128 words ($FFAF80-$FFAFFF) of the Program ROM are reserved for Motorola use. This memory area is reserved for use as expansion area for the bootstrap ROM as well as for testing purposes. Customer code should not use this area. The contents of this Program ROM segment is defined by the Bootstrap ROM Contents on page Appendix A-1.

  • Page 161: External Memory Support

    5.1.5 EXTERNAL MEMORY SUPPORT The DSP56367 does not support the SSRAM memory type. It does support SRAM and DRAM as indicated in the DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication DSP56300FM/AD. Also, care should be taken when accessing external memory to ensure that the necessary address lines are available.

  • Page 162: Internal I/o Memory Map

    Internal I/O Memory Map INTERNAL I/O MEMORY MAP The DSP56367 on-chip peripheral modules have their register files programmed to the addresses in the internal X-I/O memory range (the top 128 locations of the X data memory space) and internal Y-I/O memory range (48 locations of the Ydata memory space) as shown in Table 5-4.

  • Page 163

    HOST PORT CONTROL REGISTER (HPCR) X:$FFFFC3 HOST STATUS REGISTER (HSR) X:$FFFFC2 HOST CONTROL REGISTER (HCR) X:$FFFFC1 RESERVED X:$FFFFC0 RESERVED PORT C X:$FFFFBF PORT C CONTROL REGISTER (PCRC) X:$FFFFBE PORT C DIRECTION REGISTER (PRRC) X:$FFFFBD PORT C GPIO DATA REGISTER (PDRC) MOTOROLA DSP56367 5-15...

  • Page 164

    X:$FFFF98 RESERVED X:$FFFF97 RESERVED X:$FFFF96 RESERVED X:$FFFF95 RESERVED X:$FFFF94 SHI RECEIVE FIFO (HRX) X:$FFFF93 SHI TRANSMIT REGISTER (HTX) X:$FFFF92 SHI I C SLAVE ADDRESS REGISTER (HSAR) X:$FFFF91 SHI CONTROL/STATUS REGISTER (HCSR) X:$FFFF90 SHI CLOCK CONTROL REGISTER (HCKR) 5-16 DSP56367 MOTOROLA...

  • Page 165

    Y:$FFFFA8 RESERVED Y:$FFFFA7 RESERVED Y:$FFFFA6 RESERVED Y:$FFFFA5 RESERVED Y:$FFFFA4 RESERVED Y:$FFFFA3 RESERVED Y:$FFFFA2 RESERVED Y:$FFFFA1 RESERVED Y:$FFFFA0 RESERVED PORT E Y:$FFFF9F PORT E CONTROL REGISTER (PCRE) Y:$FFFF9E PORT E DIRECTION REGISTER(PPRE) Y:$FFFF9D PORT E GPIO DATA REGISTER(PDRE) MOTOROLA DSP56367 5-17...

  • Page 166

    ESAI_1 TRANSMIT DATA REGISTER 5 (TX5_1) Y:$FFFF84 ESAI_1 TRANSMIT DATA REGISTER 4 (TX4_1) Y:$FFFF83 ESAI_1 TRANSMIT DATA REGISTER 3 (TX3_1) Y:$FFFF82 ESAI_1 TRANSMIT DATA REGISTER 2 (TX2_1) Y:$FFFF81 ESAI_1 TRANSMIT DATA REGISTER 1 (TX1_1) Y:$FFFF80 ESAI_1 TRANSMIT DATA REGISTER 0 (TX0_1) 5-18 DSP56367 MOTOROLA...

  • Page 167: Section 6 Core Configuration

    SECTION CORE CONFIGURATION INTRODUCTION This chapter contains DSP56300 core configuration information details specific to the DSP56367. These include the following: • Operating modes • Bootstrap program • Interrupt sources and priorities • DMA request sources • • PLL control register •...

  • Page 168: Operating Mode Register (omr)

    OPERATING MODE REGISTER (OMR) The contents of the Operating Mode Register (OMR) are shown in Table 6-1. Refer to the DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication DSP56300FM/AD for a description of the OMR bits. Table 6-1 Operating Mode Register (OMR)

  • Page 169: Address Tracing Enable (ate) - Bit 15

    3. initialize TAGs to different values by unlock eight different external sectors 4. lock the PATCH sector(s) 5. move new code to locked sector(s), to the addresses that should be replaced 6. start regular PROM program ;**************************************************************************** ; PATCH initialization example ;**************************************************************************** page 132,55,0,0,0 nolist INCLUDE "ioequ.asm" INCLUDE "intequ.asm" MOTOROLA DSP56367...

  • Page 170

    ; values endm plock (r2) ; lock patch’s sector ; (start/mid/end) move #PATCH_DATA_START,r1 ; replace ROM code by PATCH #(PATCH_DATA_END-PATCH_DATA_START+1),PATCH_LOOP movem p:(r1)+,x0 movem x0,p:(r2)+ ; Do-loop restriction PATCH_LOOP #M_PROMS ; start ROM code execution ENDTEST ENDTEST ; patch data DSP56367 MOTOROLA...

  • Page 171: Operating Modes

    MODA, MODB, MODC and MODD pins during reset. Each operating mode is briefly described below. Except for modes 0 and 8, the operation of all other modes is defined by the Bootstrap ROM source code in Bootstrap ROM Contents on page Appendix A-1. Table 6-2 DSP56367 Operating Modes Reset Mode...

  • Page 172

    Host Flag 0 (HF0). This will start execution of the loaded program from the specified starting address. As in Mode C, but HDI08 is set for interfacing to Motorola HC11 microcontroller in non-multiplexed mode Mode D...

  • Page 173: Interrupt Priority Registers

    Core Configuration Interrupt Priority Registers Table 6-3 DSP56367 Mode Descriptions As in Mode C, but HDI08 is set for interfacing to Motorola 68302 bus. Mode F INTERRUPT PRIORITY REGISTERS There are two interrupt priority registers in the DSP56367: 1. IPR-C is dedicated for DSP56300 Core interrupt sources.

  • Page 174

    IRQC IPL IRQC mode IRQD IPL IRQD mode D5L1 D5L0 D4L1 D4L0 D3L1 D3L0 D2L1 D2L0 D1L1 D1L0 D0L1 D0L0 DMA0 IPL DMA1 IPL DMA2 IPL DMA3 IPL DMA4 IPL DMA5 IPL Figure 6-2 Interrupt Priority Register C DSP56367 MOTOROLA...

  • Page 175

    ESAI Transmit Last Slot ESAI Transmit Even Data ESAI Transmit Data SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty HOST Command Interrupt HOST Receive Data Interrupt MOTOROLA DSP56367...

  • Page 176

    ESAI_1 Receive Even Data ESAI_1 Receive Data ESAI_1 Receive Last Slot ESAI_1 Transmit Data with Exception Status ESAI_1 Transmit Last Slot ESAI_1 Transmit Even Data Lowest ESAI_1 Transmit Data Table 6-6 DSP56367 Interrupt Vectors Interrupt Interrupt Priority Interrupt Source Starting Address Level Range...

  • Page 177

    Core Configuration Interrupt Priority Registers Table 6-6 DSP56367 Interrupt Vectors (Continued) Interrupt Interrupt Priority Interrupt Source Starting Address Level Range VBA:$16 0 - 2 IRQD VBA:$18 0 - 2 DMA Channel 0 VBA:$1A 0 - 2 DMA Channel 1 VBA:$1C...

  • Page 178

    Core Configuration Interrupt Priority Registers Table 6-6 DSP56367 Interrupt Vectors (Continued) Interrupt Interrupt Priority Interrupt Source Starting Address Level Range VBA:$58 0 - 2 TIMER1 Compare VBA:$5A 0 - 2 TIMER1 Overflow VBA:$5C 0 - 2 TIMER2 Compare VBA:$5E 0 - 2...

  • Page 179: Dma Request Sources

    SHI FIFO Not Empty 01111 SHI FIFO Full 10000 HDI08 Receive Data 10001 HDI08 Transmit Data 10010 TIMER0 (TCF=1) 10011 TIMER1 (TCF=1) 10100 TIMER2 (TCF=1) 10101 ESAI_1 Receive Data (RDF=1) 10110 ESAI_1 Transmit Data (TDE=1) 10111-11111 RESERVED MOTOROLA DSP56367 6-13...

  • Page 180: Pll Initialization

    The Crystal Range (XTLR) bit controls the on-chip crystal oscillator transconductance. The on-chip crystal oscillator is not used on the DSP56367 since no XTAL pin is available. The XTLR bit is set to zero during hardware reset in the DSP56367.

  • Page 181: Jtag Identification (id) Register

    00000001110 JTAG BOUNDARY SCAN REGISTER (BSR) The boundary scan register (BSR) in the DSP56367 JTAG implementation contains bits for all device signal and clock pins and associated control signals. All bidirectional pins have a single register bit in the boundary scan register for pin data, and are controlled by an associated control bit in the boundary scan register.

  • Page 182

    Core Configuration JTAG Boundary Scan Register (BSR) Table 6-10 DSP56367 BSR Bit Definition (Continued) BSR Cell BSR Cell Pin Name Pin Type Pin Name Pin Type Type Type IRQD Input Data HAD0 Control Input/Output Data HAD0 Input/Output Data Input/Output Data...

  • Page 183

    Core Configuration JTAG Boundary Scan Register (BSR) Table 6-10 DSP56367 BSR Bit Definition (Continued) BSR Cell BSR Cell Pin Name Pin Type Pin Name Pin Type Type Type Output3 Data 112 HREQ/HTRQ Input/Output Data Output3 Data 113 HACK/RRQ Control Output3...

  • Page 184

    Core Configuration JTAG Boundary Scan Register (BSR) Table 6-10 DSP56367 BSR Bit Definition (Continued) BSR Cell BSR Cell Pin Name Pin Type Pin Name Pin Type Type Type FSR_1 Input/Output Data 143 HREQ Control RD,WR Control 144 HREQ Input/Output Data...

  • Page 185: Section 7 General Purpose Input/output

    GENERAL PURPOSE INPUT/OUTPUT INTRODUCTION The DSP56367 provides up to 37 bidirectional signals that can be configured as GPIO signals or as peripheral dedicated signals. No dedicated GPIO signals are provided. All of these signals are GPIO by default after reset. The techniques for register programming for all GPIO functionality is very similar between these interfaces.

  • Page 186: Port C Signals And Registers

    The timer/event counter signal (TIO), when not used as a timer signal can be configured as a GPIO signal. The signal is controlled by the appropriate timer control status register (TCSR). The register is described in Section 13 - Timer/ Event Counter. DSP56367 MOTOROLA...

  • Page 187: Section 8 Host Interface (hdi08)

    – Registers are directly mapped into eight internal X data memory locations • Data Word: – 24-bit (native) data words are supported, as are 8-bit and 16-bit words • Transfer Modes: – DSP to Host – Host to DSP MOTOROLA DSP56367...

  • Page 188: Interface - Host Side

    – HRW/HRD Read/write select (HRW) or Read Strobe (HRD) – HDS/HWR Data Strobe (HDS) or Write Strobe (HWR) – HCS/HA10 Host chip select (HCS) or Host address line HA10 – HOREQ/HTRQ Host request (HOREQ) or Host transmit request (HTRQ) DSP56367 MOTOROLA...

  • Page 189

    • Real-Time Production Diagnostics • Debugging Window for Program Development • Host Control Protocols • Interface Capabilities: – Glueless interface (no external logic required) to the following: • Motorola HC11 • Hitachi H8 • 8051 family MOTOROLA DSP56367...

  • Page 190: Hdi08 Host Port Signals

    – Minimal glue-logic (pullups, pulldowns) required to interface to the following: • ISA bus • Motorola 68K family • Intel X86 family. HDI08 HOST PORT SIGNALS The host port signals are described in Section 2. If the Host Interface functionality is not required, the 16 pins may be defined as general purpose I/O pins PB0-PB15.

  • Page 191: Hdi08 Block Diagram

    Host Port Control Register Interrupt Vector Register HBAR Host Base Address register RXH/RXM/RXL Receive Register High/Middle/Low HOTX Host Transmit register TXH/TXM/TXL Transmit Register High/Middle/Low HORX Host Receive register HDDR Host Data Direction Register Host Data Register Figure 8-1 HDI08 Block Diagram MOTOROLA DSP56367...

  • Page 192: Hdi08 – Dsp-side Programmer's Model

    The 24-bit read-only HORX register is used for host-to-DSP data transfers. The HORX register is loaded with 24-bit data from the transmit data registers (TXH:TXM:TXL) on the host side when both the transmit data register empty TXDE (host side) and host receive data DSP56367 MOTOROLA...

  • Page 193: Host Transmit Data Register (hotx)

    If the programmer reads any of those status bits within the next two cycles, the bit will not reflect its current status. See the DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication DSP56300FM/AD for further details. 8.5.3 HOST CONTROL REGISTER (HCR) The HCR is 16-bit read/write control register used by the DSP core to control the HDI08 operating mode.

  • Page 194: Hcr Host Transmit Interrupt Enable (htie) Bit 1

    RREQ control bits are used for host processor interrupt control via the external HOREQ output signal (or HRREQ and HTREQ output signals if HDREQ in the ICR is set). Also, in the non-DMA mode, the HACK input signal is used for the MC68000 Family vectored DSP56367 MOTOROLA...

  • Page 195

    HOREQ signal to request data transfer. The HACK input signal is used as a DMA transfer acknowledge input. If the DMA direction is from DSP to host, the contents of the selected register are driven onto the host data bus MOTOROLA DSP56367...

  • Page 196: Hcr Reserved Bits 8-15

    The HRDF bit indicates that the host receive data register (HORX) contains data from the host processor. HRDF is set when data is transferred from the TXH:TXM:TXL registers to the HORX register. HRDF is cleared when HORX is read by the DSP core. If HRDF is set the 8-10 DSP56367 MOTOROLA...

  • Page 197: Hsr Host Transmit Data Empty (htde) Bit 1

    ICR bits HM1 and HM0 • Either or both of the HCR bits HDM1 and HDM0 have been set When the DMA bit is zero, the channel not in use can be used for polled or interrupt operation by the DSP. MOTOROLA DSP56367 8-11...

  • Page 198: Host Base Address Register (hbar)

    These bits are reserved. They read as zero and should be written with zero for future compatibility. HAD[0-7] Latch A[3:7] HA[8:10] Chip select Base DSP Peripheral Address 8 bits data bus register BA[3:7] Figure 8-5 Self Chip Select logic 8-12 DSP56367 MOTOROLA...

  • Page 199: Host Port Control Register (hpcr)

    (HMUX=0), and as host address line 10 (HA10) in the multiplexed bus mode (HMUX=1). If this bit is cleared, then HCS/HA10 is configured as GPIO pin according to the value of HDDR and HDR registers. MOTOROLA DSP56367 8-13...

  • Page 200: Hpcr Host Request Enable (hren) Bit 4

    If HDSP is set, the data strobe signals are configured as active high inputs, and data is transferred when the data strobe is high. The data strobe signals are either HDS by itself or HRD and HWR together. 8-14 DSP56367 MOTOROLA...

  • Page 201: Hpcr Host Address Strobe Polarity (hasp) Bit 10

    Write cycle Read data out Data Read cycle In the dual strobe bus mode, there are separate HRD and HWR signals that specify the access as being a read or write access, respectively. Figure 8-8 Dual strobes bus MOTOROLA DSP56367 8-15...

  • Page 202: Hpcr Host Chip Select Polarity (hcsp) Bit 13

    Section 8.6.8. If bit DRxx is set, the corresponding HDI08 pin is configured as an output signal. If bit DRxx is cleared, the corresponding HDI08 pin is configured as an input signal. See Table 8-6. Figure 8-9 Host Data Direction Register (HDDR) (X:$FFFFC8) DR15 DR14 DR13 DR12 DR11 DR10 8-16 DSP56367 MOTOROLA...

  • Page 203: Host Data Register (hdr)

    Table 8-7 shows the results of the four reset types on the bits in each of the HDI08 registers accessible by the DSP core. The hardware reset (HW) is caused by the RESET signal. The software reset (SW) is caused by executing the RESET instruction. The individual reset (IR) MOTOROLA DSP56367 8-17...

  • Page 204: Host Interface Dsp Core Interrupts

    Transmit data register empty • Receive data register full Although there is a set of vectors reserved for host command use, the host command can access any interrupt vector in the interrupt vector table. The DSP interrupt service routine 8-18 DSP56367 MOTOROLA...

  • Page 205: Hdi08 – External Host Programmer's Model

    The HDI08 appears to the host processor as a memory-mapped peripheral occupying 8 bytes in the host processor address space (See Table 8-8). The eight HDI08 include the following: • A control register (ICR) • A status register (ISR) • Three data registers (RXH/TXH, RXM/TXM and RXL/TXL) MOTOROLA DSP56367 8-19...

  • Page 206

    Unused RXH/TXH RXL/TXL Receive/Transmit RXM/TXM RXM/TXM Bytes RXL/TXL RXH/TXH Host Data Bus Host Data Bus H0 - H7 H0 - H7 Note: The RXH/TXH register is always mapped to the most significant byte of the DSP word. 8-20 DSP56367 MOTOROLA...

  • Page 207: Interface Control Register (icr)

    (HOREQ or HTRQ) signal when the transmit data register empty (TXDE) status bit in the ISR is set. If TREQ is cleared, TXDE requests are disabled. If TREQ is set, the host request signal (HOREQ or HTRQ) is asserted if TXDE is set. MOTOROLA DSP56367 8-21...

  • Page 208: Icr Double Host Request (hdrq) Bit 2

    The HF0 bit is used as a general purpose flag for host-to-DSP communication. HF0 may be set or cleared by the host processor and cannot be changed by the DSP core. HF0 is reflected in the HSR on the DSP side of the HDI08. 8-22 DSP56367 MOTOROLA...

  • Page 209: Icr Host Flag 1 (hf1) Bit 4

    DSP to host, the contents of the selected register are enabled onto the host data bus when HACK is asserted. If the DMA direction is from host to DSP, the selected register is written from the host data bus when HACK is asserted. MOTOROLA DSP56367 8-23...

  • Page 210: Icr Initialize Bit (init) Bit 7

    Table 8-13 INIT Command Effect TREQ RREQ After INIT Execution Transfer Direction Initialized INIT=0 None INIT=0; RXDF=0; HTDE=1 DSP to Host INIT=0; TXDE=1; HRDF=0 Host to DSP INIT=0; RXDF=0; HTDE=1; TXDE=1; HRDF=0 Host to/from DSP 8-24 DSP56367 MOTOROLA...

  • Page 211: Command Vector Register (cvr)

    The ISR is an 8-bit read-only status register used by the host processor to interrogate the status and flags of the HDI08. The host processor can write to this address without affecting the internal state of the HDI08, which is useful if the user desires to access all of the HDI08 MOTOROLA DSP56367 8-25...

  • Page 212: Isr Receive Data Register Full (rxdf) Bit 0

    ISR Host Flag 2 (HF2) Bit 3 The HF2 bit in the ISR indicates the state of host flag 2 in the HCR on the DSP side. HF2 can be changed only by the DSP (see Section 8.5.3.4). 8-26 DSP56367 MOTOROLA...

  • Page 213: Isr Host Flag 3 (hf3) Bit 4

    HOREQ and HACK signals are asserted. The contents of this register are initialized to $0F by hardware or software reset, which corresponds to the uninitialized interrupt vector in the MC68000 Family. Figure 8-15 Interrupt Vector Register (IVR) MOTOROLA DSP56367 8-27...

  • Page 214: Receive Byte Registers (rxh:rxm:rxl)

    Writing to the data register at host address $7 clears the TXDE bit. The contents of the transmit byte registers are transferred as 24-bit data to the HORX register when both TXDE and the HRDF bit are cleared. This transfer operation sets TXDE and HRDF. 8-28 DSP56367 MOTOROLA...

  • Page 215: Host Side Registers After Reset

    HDI08 functionality. If the HDI08 is in GPIO mode, the HDDR configures each corresponding signal in the HDR as an input signal if the HDDR bit is cleared or as an output signal if the HDDR bit is set (see Section 8.5.7 and Section 8.5.8). MOTOROLA DSP56367 8-29...

  • Page 216: Servicing The Host Interface

    Data written by the host processor is transferred directly to the DSP side. ≠ • 4. If (HF2 HF3) 0, depending on how the host flags have been defined, may indicate an application-specific state within the DSP core has been reached. Intervention by the host processor may be required. 8-30 DSP56367 MOTOROLA...

  • Page 217: Servicing Interrupts

    The host processor can test RXDF and TXDE to determine the interrupt source. The host processor interrupt service routine must read or write the appropriate HDI08 data register to clear the interrupt. HOREQ/HTRQ and/or HRRQ is deasserted under the following conditions: MOTOROLA DSP56367 8-31...

  • Page 218

    HACK. The contents of the IVR are placed on the host data bus while HOREQ and HACK are simultaneously asserted. The IVR data tells the MC680XX host processor which interrupt routine to execute to service the DSP. 8-32 DSP56367 MOTOROLA...

  • Page 219: Section 9 Serial Host Interface

    DSP and an external host processor. The SHI can also communicate with other serial peripheral devices. The SHI supports two well-known and widely used synchronous serial buses: the Motorola Serial Peripheral Interface (SPI) bus and the Philips Inter-Integrated-Circuit Control (I C) bus.

  • Page 220: Serial Host Interface Internal Architecture

    The host side invokes the SHI for communication and data transfer with the DSP through a shift register that may be accessed serially using either the I C or the SPI bus protocols. Figure 9-1 shows the SHI block diagram. DSP56367 MOTOROLA...

  • Page 221: Characteristics Of The Spi Bus

    When the SPI is configured as a master, MISO is the master data input line, and MOSI is the master data output line. When the SPI is configured as a slave device, MISO is the slave data output line, and MOSI is the slave data input line. MOTOROLA DSP56367...

  • Page 222: Shi Clock Generator

    Divide By 256 HMST = 1 HDM0–HDM7 CPHA, CPOL, HI AA0417 Figure 9-2 SHI Clock Generator SERIAL HOST INTERFACE PROGRAMMING MODEL The Serial Host Interface programming model has two parts: • Host side—see Figure 9-3 below and Section 9.5.1 DSP56367 MOTOROLA...

  • Page 223

    Serial Host Interface Serial Host Interface Programming Model • DSP side—see Figure 9-4 and Section 9.5.2 through Section 9.5.6 for detailed information. I/O Shift Register (IOSR) IOSR AA0418 Figure 9-3 SHI Programming Model—Host Side MOTOROLA DSP56367...

  • Page 224

    Serial Host Interface Serial Host Interface Programming Model Figure 9-4 SHI Programming Model—DSP Side DSP56367 MOTOROLA...

  • Page 225: Shi Input/output Shift Register (iosr)—host Side

    MSB first. In 8-bit data transfer modes, the most significant byte of the IOSR is used as the shift register. In 16-bit data transfer modes, the two most significant bytes become the shift register. In 24-bit transfer modes, the shift register uses all three bytes of the IOSR (see Figure 9-5). MOTOROLA DSP56367...

  • Page 226: Shi Host Transmit Data Register (htx)—dsp Side

    HRX (the other bits are cleared); in the 16-bit mode the two most significant bytes are transferred (the least significant byte is cleared), and in the 24-bit mode, all 24 bits are transferred to the HRX. The HRX may be read by the DSP while the FIFO is DSP56367 MOTOROLA...

  • Page 227: Shi Slave Address Register (hsar)—dsp Side

    (it is an illegal combination). The HCKR bits are cleared during hardware reset or software reset, except for CPHA, which is set. The HCKR is not affected by the stop state. The HCKR bits are described in the following paragraphs. MOTOROLA DSP56367...

  • Page 228: Clock Phase And Polarity (cpha And Cpol)—bits 1–0

    It has its greatest impact on the first bit transmitted (MSB) in that it does or does not allow a clock transition before the data capture edge. 9-10 DSP56367 MOTOROLA...

  • Page 229: Hckr Prescaler Rate Select (hrs)—bit 2

    C when HCKFR is set). The HDM[7:0] bits are cleared during hardware reset and software reset. Note: Use the equations in the SHI datasheet to determine the value of HDM[7:0] for the specific serial clock frequency required. MOTOROLA DSP56367 9-11...

  • Page 230: Hckr Reserved Bits—bits 23–14, 11

    HCSR or the CPOL bit in the HCKR, while the filter mode bits are in a non-bypass mode (HFM[1:0] not equal to ‘00’), the programmer should wait at least ten times the tolerable spike width before enabling the SHI (setting HEN in the HCSR). 9-12 DSP56367 MOTOROLA...

  • Page 231: Shi Control/status Register (hcsr)—dsp Side

    Table 9-4. HM[1:0] should be modified only when the SHI is idle (HBUSY = 0). HM[1:0] are cleared during hardware reset and software reset. Table 9-4 SHI Data Size Description 8-bit data 16-bit data 24-bit data Reserved MOTOROLA DSP56367 9-13...

  • Page 232: Hcsr Fifo-enable Control (hfifo)—bit 5

    C bus by generating start events, clock pulses, and stop events for transmission and reception of serial data. It is recommended that an SHI individual reset be generated (HEN cleared) before changing HMST. HMST is cleared during hardware reset and software reset. 9-14 DSP56367 MOTOROLA...

  • Page 233: Hcsr Host-request Enable (hrqe[1:0])—bits 8–7

    Setting HIDLE causes a stop event after receiving the current word. HIDLE is set while the SHI is not in the I C master mode, while the chip is in the stop state, and during hardware reset, software reset and individual reset. MOTOROLA DSP56367 9-15...

  • Page 234: Hcsr Bus-error Interrupt Enable (hbie)—bit 10

    Table 9-6 HCSR Receive Interrupt Enable Bits HRIE[1:0] Interrupt Condition Disabled Not applicable Receive FIFO not empty HRNE = 1 and HROE = 0 Receive Overrun Error HROE = 1 Reserved Not applicable 9-16 DSP56367 MOTOROLA...

  • Page 235: Hcsr Host Transmit Underrun Error (htue)—bit 14

    SHI individual reset, and during the stop state. 9.5.6.14 HCSR Reserved Bits—Bits 23, 18 and 16 These bits are reserved. They read as zero and should be written with zero for future compatibility. MOTOROLA DSP56367 9-17...

  • Page 236: Host Receive Fifo Not Empty (hrne)—bit 17

    SPI mode, HBUSY is set while SS is asserted. When operating in the master SPI mode, HBUSY is set if the HTX register is not empty or if the IOSR is not empty. 9-18 DSP56367 MOTOROLA...

  • Page 237: Characteristics Of The I 2 C Bus

    Bus not busy—Both data and clock lines remain high. • Start data transfer—The start event is defined as a change in the state of the data line, from high to low, while the clock is high (see Figure 9-8). MOTOROLA DSP56367 9-19...

  • Page 238

    (see Figure 9-9). Start Clock Pulse For Event Acknowledgment SCL From Master Device Data Output by Transmitter Data Output by Receiver AA0424 Figure 9-9 Acknowledgment on the I C Bus 9-20 DSP56367 MOTOROLA...

  • Page 239

    Slave Device Slave Device Slave Device Slave Address First Data Byte Data Byte S, P N = 0 to M Data Bytes Start Start or Stop Bit AA0425 Figure 9-10 I C Bus Protocol For Host Write Cycle MOTOROLA DSP56367 9-21...

  • Page 240: Shi Programming Considerations

    SHI external pins operate as follows: • SCK/SCL is the SCK serial clock input. • MISO/SDA is the MISO serial data output. • MOSI/HA0 is the MOSI serial data input. • SS/HA2 is the SS slave select input. 9-22 DSP56367 MOTOROLA...

  • Page 241: Spi Master Mode

    SPI master device, the programmer should program the proper clock rate, phase and polarity in HCKR. When configured in the SPI master mode, the SHI external pins operate as follows: • SCK/SCL is the SCK serial clock output. • MISO/SDA is the MISO serial data input. MOTOROLA DSP56367 9-23...

  • Page 242

    C slave mode is entered by enabling the SHI (HEN=1), selecting the I C mode C=1), and selecting the slave mode of operation (HMST=0). In this operational mode the contents of HCKR are ignored. When configured in the I C slave mode, the SHI external pins operate as follows: 9-24 DSP56367 MOTOROLA...

  • Page 243

    C master device may terminate this session by generating a stop event. If HCKFR is set, when the HRX FIFO is full the SHI holds the clock line to GND not letting the master device write to IOSR, which eliminates the possibility of reaching the overrun condition. MOTOROLA DSP56367 9-25...

  • Page 244

    The HREQ line may be used to interrupt the external I C master device. Connecting the HREQ line between two SHI-equipped DSPs, one operating as an I master device and the other as an I C slave device, enables full hardware handshaking. 9-26 DSP56367 MOTOROLA...

  • Page 245

    C master device if HRQE[1:0] are cleared, and considered if either of them is set. When asserted, HREQ indicates that the external slave device is ready for the next data transfer. As a result, the I C master device sends clock pulses MOTOROLA DSP56367 9-27...

  • Page 246

    HTX contents are transferred to the IOSR when the complete word (according to HM[1:0]) has been shifted out. It is, therefore, the responsibility of the programmer to select the right 9-28 DSP56367 MOTOROLA...

  • Page 247: Shi Operation During Dsp Stop

    The HCSR status bits and the transmit/receive paths are reset to the same state produced by hardware reset or software reset. • The HCSR and HCKR control bits are not affected. Note: It is recommended that the SHI be disabled before entering the stop state. MOTOROLA DSP56367 9-29...

  • Page 248

    Serial Host Interface SHI Programming Considerations 9-30 DSP56367 MOTOROLA...

  • Page 249: Section 10 Enhanced Serial Audio Interface (esai)

    It is a superset of the 56300 Family ESSI peripheral and of the 56000 Family SAI peripheral. Note: The DSP56367 has two ESAI modules. This section describes the ESAI, and Section 11 describes the ESAI_1. The ESAI and ESAI_1 share 4 data pins. This is described in the ESAI_1 section.

  • Page 250

    SDO1 [PC10] Shift Register RCCR SDO2/SDI3 [PC9] Shift Register TCCR SDO3/SDI2 [PC8] SAICR Shift Register SAISR SDO4/SDI1 [PC7] Shift Register Clock / Frame Sync Generators RCLK Control Logic SDO5/SDI0 [PC6] Shift Register TCLK Figure 10-1 ESAI Block Diagram 10-2 DSP56367 MOTOROLA...

  • Page 251: Esai Data And Control Pins

    SDO2/SDI3 is used as the SDO2 for transmitting data from the TX2 serial transmit shift register when programmed as a transmitter pin, or as the SDI3 signal for receiving serial data to the RX3 serial receive shift register when programmed as a receiver pin. SDO2/SDI3 is an MOTOROLA DSP56367 10-3...

  • Page 252: Serial Transmit 3/receive 2 Data Pin (sdo3/sdi2)

    If a data word follows immediately, there is no high-impedance interval. SDO4/SDI1 may be programmed as a general-purpose I/O pin (PC7) when the ESAI SDO4 and SDI1 functions are not being used. 10-4 DSP56367 MOTOROLA...

  • Page 253: Serial Transmit 5/receive 0 Data Pin (sdo5/sdi0)

    Although the external ESAI serial clock can be independent of and asynchronous to the DSP system clock, the DSP clock frequency must be at least three times the external ESAI serial clock frequency and each ESAI serial clock phase must exceed the minimum of 1.5 DSP clock periods. MOTOROLA DSP56367 10-5...

  • Page 254: Transmitter Serial Clock (sckt)

    SCKT is a bidirectional pin providing the transmitters serial bit clock for the ESAI interface. The direction of this pin is determined by the TCKD bit in the TCCR register. The SCKT is a clock input or output used by all the enabled transmitters in the asynchronous mode (SYN=0) 10-6 DSP56367 MOTOROLA...

  • Page 255: Frame Sync For Receiver (fsr)

    RCCR register. When configured as the output flag OF1, this pin reflects the value of the OF1 bit in the SAICR register, and the data in the OF1 bit shows up at the pin synchronized to the frame sync being used by the transmitter and receiver sections. When configured as the MOTOROLA DSP56367 10-7...

  • Page 256: Frame Sync For Transmitter (fst)

    HCKR is a bidirectional pin providing the receivers high frequency clock for the ESAI interface. The direction of this pin is determined by the RHCKD bit in the RCCR register. In the asynchronous mode (SYN=0), the HCKR pin operates as the high frequency clock input 10-8 DSP56367 MOTOROLA...

  • Page 257: Esai Programming Model

    The read/write Transmitter Clock Control Register (TCCR) controls the ESAI transmitter clock generator bit and frame sync rates, the bit clock and high frequency clock sources and the directions of the HCKT, FST and SCKT signals. (See Figure 10-2). In the synchronous MOTOROLA DSP56367 10-9...

  • Page 258: Tccr Transmit Prescale Modulus Select (tpm7–tpm0) - Bits 0–7

    (SCKT) pin of the DSP. The bit clock output is also available internally for use as the bit clock to shift the transmit and receive shift registers. The ESAI transmit clock generator functional diagram is shown in Figure 10-3. 10-10 DSP56367 MOTOROLA...

  • Page 259

    DIVIDE BY 1 DIVIDE BY 1 DIVIDE TO DIVIDE BY TO DIVIDE BY BY 2 DIVIDE BY 8 THCKD=1 Notes: 1. F is the DSP56300 Core internal clock frequency. Figure 10-3 ESAI Clock Generator Functional Block Diagram MOTOROLA DSP56367 10-11...

  • Page 260: Tccr Transmit Prescaler Range (tpsr) - Bit 8

    1 to 32 (TDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of 1 (TDC[4:0]=00000) provides continuous periodic data word transfers. A bit-length frame sync (TFSL=1) must be used in this case. The ESAI frame sync generator functional diagram is shown in Figure 10-4. 10-12 DSP56367 MOTOROLA...

  • Page 261: Tccr Tx High Frequency Clock Divider (tfp3-tfp0) - Bits 14–17

    TFP3-TFP0 bits specify an additional division ratio in the clock divider chain. See Table 10-3 for the specification of the divide ratio. The ESAI high frequency clock generator functional diagram is shown in Figure 10-3. MOTOROLA DSP56367 10-13...

  • Page 262: Tccr Transmit Clock Polarity (tckp) - Bit 18

    SCKT pin. When TCKD is cleared, the clock source is external; the internal clock generator is disconnected from the SCKT pin, and an external clock source may drive this pin. See Table 10-2. 10-14 DSP56367 MOTOROLA...

  • Page 263: Tccr Transmit Frame Sync Signal Direction (tfsd) - Bit 22

    #0). The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one. MOTOROLA DSP56367 10-15...

  • Page 264: Tcr Esai Transmit 1 Enable (te1) - Bit 1

    In the network mode, the operation of clearing TE2 and setting it again disables the transmitter #2 after completing transmission of the current data word until the beginning of the next frame. During that time period, the SDO2/SDI3 pin remains in the high-impedance 10-16 DSP56367 MOTOROLA...

  • Page 265: Tcr Esai Transmit 3 Enable (te3) - Bit 3

    In the network mode, the operation of clearing TE4 and setting it again disables the transmitter #4 after completing transmission of the current data word until the beginning of the next frame. During that time period, the SDO4/SDI1 pin remains in the high-impedance MOTOROLA DSP56367 10-17...

  • Page 266: Tcr Esai Transmit 5 Enable (te5) - Bit 5

    1. If the data word is left-aligned (TWA=0), and zero padding is disabled (PADC=0), then the last data bit is repeated after the data word has been transmitted. If zero padding is enabled (PADC=1), zeroes are transmitted after the data word has been transmitted. 10-18 DSP56367 MOTOROLA...

  • Page 267

    16 bits long, and the next 12 slots and words will be 20 bits long, as required by the AC97 protocol. Table 10-4 Transmit Network Mode Selection TMOD1 TMOD0 TDC4-TDC0 Transmitter Network Mode $0-$1F Normal Mode On-Demand Mode $1-$1F Network Mode Reserved AC97 MOTOROLA DSP56367 10-19...

  • Page 268

    Enhanced Serial Audio Interface (ESAI) ESAI Programming Model Figure 10-6 Normal and Network Operation 10-20 DSP56367 MOTOROLA...

  • Page 269

    The possible combinations are shown in Table 10-5. See also the ESAI data path programming model in Figure 10-13 and Figure 10-14. Table 10-5 ESAI Transmit Slot and Word Length Selection TSWS4 TSWS3 TSWS2 TSWS1 TSWS0 SLOT LENGTH WORD LENGTH MOTOROLA DSP56367 10-21...

  • Page 270

    The TFSL bit selects the length of frame sync to be generated or recognized. If TFSL is cleared, a word-length frame sync is selected. If TFSL is set, a 1-bit clock period frame sync is selected. See Figure 10-7 for examples of frame length selection. 10-22 DSP56367 MOTOROLA...

  • Page 271

    DATA TX FRAME SYNC TX SERIAL DATA DATA DATA MIXED FRAME LENGTH: TFSL=0, RFSL=1 SERIAL CLOCK RX FRAME SYNC RX SERIAL DATA DATA DATA TX FRAME SYNC TX SERIAL DATA DATA DATA Figure 10-7 Frame Length Selection MOTOROLA DSP56367 10-23...

  • Page 272: Tcr Transmit Frame Sync Relative Timing (tfsr) - Bit 16

    The transmitter clock outputs drive zeroes while in the personal reset state. Note that to leave the personal reset state by clearing TPR, the procedure described in Section 10.6, “ESAI Initialization Examples” should be followed. 10-24 DSP56367 MOTOROLA...

  • Page 273: Tcr Transmit Exception Interrupt Enable (teie) - Bit 20

    When TLIE is cleared the transmit last slot interrupt is disabled. TLIE is disabled when TDC[4:0]=$00000 (on-demand mode). The use of the transmit last slot interrupt is described in Section 10.4.3, “ESAI Interrupt Requests”. MOTOROLA DSP56367 10-25...

  • Page 274: Esai Receive Clock Control Register (rccr)

    DSP clock as source (RHCKD=1 or RCKD=1). 10.3.3.3 RCCR Rx Frame Rate Divider Control (RDC4–RDC0) - Bits 9–13 The RDC4–RDC0 bits control the divide ratio for the programmable frame rate dividers used to generate the receiver frame clocks. 10-26 DSP56367 MOTOROLA...

  • Page 275: Rccr Receiver Frame Sync Polarity (rfsp) - Bit 19

    When RFSP is cleared the frame sync signal polarity is positive (i.e the frame start is indicated by a high level on the frame sync pin). When RFSP is set the frame sync signal polarity is negative (i.e the frame start is indicated by a low level on the frame sync pin). MOTOROLA DSP56367 10-27...

  • Page 276: Rccr Receiver High Frequency Clock Polarity (rhckp) - Bit 20

    FSR pin. In the asynchronous mode when RFSD is cleared, the receiver frame sync source is external; the internal clock generator is disconnected from the FSR pin, and an external clock source may drive this pin. 10-28 DSP56367 MOTOROLA...

  • Page 277: Rccr Receiver High Frequency Clock Direction (rhckd) - Bit

    In the synchronous mode when RHCKD is set, the HCKR pin becomes the OF2 output flag. If RHCKD is cleared, then the HCKR pin becomes the IF2 input flag. See Table 10-1 and Table 10-9. Table 10-9 HCKR Pin Definition Table Control Bits HCKR PIN RHCKD HCKR input HCKR output MOTOROLA DSP56367 10-29...

  • Page 278: Rcr Esai Receiver 0 Enable (re0) - Bit 0

    RX1 data register. If RE1 is set while some of the other receivers are already in operation, the first data word received in RX1 will be invalid and must be discarded. 10-30 DSP56367 MOTOROLA...

  • Page 279: Rcr Esai Receiver 2 Enable (re2) - Bit 2

    RCR Receiver Network Mode Control (RMOD1-RMOD0) - Bits 8-9 The RMOD1 and RMOD0 bits are used to define the network mode of the ESAI receivers according to Table 10-10. In the normal mode, the frame rate divider determines the word MOTOROLA DSP56367 10-31...

  • Page 280

    The possible combinations are shown in Table 10-11. See also the ESAI data path programming model in Figure 10-13 and Figure 10-14. Table 10-11 ESAI Receive Slot and Word Length Selection RSWS4 RSWS3 RSWS2 RSWS1 RSWS0 SLOT LENGTH WORD LENGTH 10-32 DSP56367 MOTOROLA...

  • Page 281: Rcr Receiver Frame Sync Length (rfsl) - Bit 15

    When in the personal reset state, the status bits are reset to the same state as after hardware reset.The control bits are not affected by the personal reset state.The receiver data pins are disconnected while in the personal reset state. Note that to leave the personal reset state by MOTOROLA DSP56367 10-33...

  • Page 282: Rcr Receive Exception Interrupt Enable (reie) - Bit 20

    When RLIE is cleared the receive last slot interrupt is disabled. Hardware and software reset clear RLIE. RLIE is disabled when RDC[4:0]=00000 (on-demand mode). The use of the receive last slot interrupt is described in Section 10.4.3, “ESAI Interrupt Requests”. 10-34 DSP56367 MOTOROLA...

  • Page 283: Esai Common Control Register (saicr)

    OF2, and data present in the OF2 bit is written to the OF2 pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode. MOTOROLA DSP56367 10-35...

  • Page 284: Saicr Reserved Bits - Bits 3-5, 9-23

    If ALC is cleared, transmitted and received word are left aligned to bit 23 in the transmit and receive shift registers. Note: While ALC is set, 20-bit and 24-bit words may not be used, and word length control should specify 8-, 12- or 16-bit words, otherwise results are unpredictable. 10-36 DSP56367 MOTOROLA...

  • Page 285

    CLOCK SYNC EXTERNAL CLOCK EXTERNAL FRAME SYNC SCKT INTERNAL CLOCK INTERNAL FRAME SYNC ESAI BIT CLOCK CLOCK FRAME SYNC RECEIVER NOTE: Transmitter and receiver have the same clocks and frame syncs. Figure 10-11 SAICR SYN Bit Operation MOTOROLA DSP56367 10-37...

  • Page 286: Esai Status Register (saisr)

    The IF2 bit is updated with this data when the receive shift registers are transferred into the receiver data registers. IF2 reads as a zero when it is not enabled. Hardware, software, ESAI individual, and STOP reset clear IF2. 10-38 DSP56367 MOTOROLA...

  • Page 287: Saisr Reserved Bits - Bits 3-5, 11-12, 18-23

    (1, 3, 5, etc.). Time slots are numbered from zero to N-1, where N is the number of time slots in the frame. RODF is set when the contents of the receive MOTOROLA DSP56367 10-39...

  • Page 288: Saisr Transmit Frame Sync Flag (tfs) - Bit 13

    TSR disabled time slot period in network mode (as if data were being transmitted after the TSR was written). When set, TEDE indicates that data should be written to all the TX 10-40 DSP56367 MOTOROLA...

  • Page 289: Saisr Transmit Odd-data Register Empty (tode) - Bit 17

    DSP writes to the TSR to disable transmission of the next time slot. If TIE is set, an ESAI transmit data interrupt request is issued when TODE is set. Hardware, software, ESAI individual, and STOP reset clear TODE. MOTOROLA DSP56367 10-41...

  • Page 290

    NOTES: (b) Transmit Registers 1. Data is sent MSB first if TSHFD=0. 2. 24-bit fractional format (ALC=0). 3. 32-bit mode is not shown. 4. Data word is left-aligned (TWA=0,PADC=0). Figure 10-13 ESAI Data Path Programming Model ([R/T]SHFD=0) 10-42 DSP56367 MOTOROLA...

  • Page 291

    (b) Transmit Registers 1. Data is sent LSB first if TSHFD=1. 2. 24-bit fractional format (ALC=0). 3. 32-bit mode is not shown. 4. Data word is left aligned (TWA=0,PADC=1). Figure 10-14 ESAI Data Path Programming Model ([R/T]SHFD=1) MOTOROLA DSP56367 10-43...

  • Page 292: Esai Receive Shift Registers

    (least significant portion, and the 8 most significant bits when ALC=1) of the TXx are don’t care bits. The DSP is interrupted whenever the TXx becomes empty if the transmit data register empty interrupt has been enabled. 10-44 DSP56367 MOTOROLA...

  • Page 293: Esai Time Slot Register (tsr)

    Figure 10-15 TSMA Register X:$FFFFBA TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16 TS31 TS30 TS29 TS28 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 10-16 TSMB Register MOTOROLA DSP56367 10-45...

  • Page 294: Receive Slot Mask Registers (rsma, Rsmb)

    (RDF=1), or to ignore the received data. RSMA and RSMB should be considered as each containing half of a 32-bit register RSM. See Table 10-17 and 10-46 DSP56367 MOTOROLA...

  • Page 295

    Data written to the RSM affects the next received frame. The frame being received is not affected by this data and would comply to the last RSM setting. Data read from RSM returns the last written data. MOTOROLA DSP56367 10-47...

  • Page 296

    The DSP programmer must use an individual ESAI reset when changing the ESAI control registers (except for TEIE, REIE, TLIE, RLIE, TIE, RIE, TE0-TE5, RE0-RE3) to ensure proper operation of the interface. 10-48 DSP56367 MOTOROLA...

  • Page 297: Esai Interrupt Requests

    (TDE=1), and a transmitter underrun error has occurred (TUE=1). TUE is cleared by first reading the SAISR and then writing to all the enabled transmit data registers, or to the TSR register. MOTOROLA DSP56367 10-49...

  • Page 298: Operating Modes – Normal, Network, And On-demand

    For the network mode, 2 to 32 time slots per frame may be selected. During each frame, 0 to 32 data words of I/O may be received/transmitted. In either case, the transfers are periodic. The frame sync signal indicates the first time slot in the frame. Network mode is typically 10-50 DSP56367 MOTOROLA...

  • Page 299: Synchronous/asynchronous Operating Modes

    1. In the word-long frame sync format, the frame sync signal is asserted during the entire word data transfer period. This frame sync length is compatible with Motorola codecs, SPI serial peripherals, serial A/D and D/A converters, shift registers, and telecommunication PCM serial I/O.

  • Page 300: Shift Direction Selection

    (TEBE=0) and its direction is selected by RFSD, RFSD=1 for output and RFSD=0 for input. Flag 2 (HCKR pin) direction is selected by RHCKD, RHCKD=1 for output and RHCKD=0 for input. 10-52 DSP56367 MOTOROLA...

  • Page 301: Gpio - Pins And Registers

    Direction Register (PRRC) controls the functionality of the ESAI GPIO pins. Each of the PC(11:0) bits controls the functionality of the corresponding port pin. See Table 10-12 for the port pin configurations. Hardware and software reset clear all PCRC bits. MOTOROLA DSP56367 10-53...

  • Page 302: Port C Direction Register (prrc)

    Reserved bit - read as zero; should be written with zero for future compatibility. Figure 10-19 PCRC Register X:$FFFFBE PDC11 PDC10 PDC9 PDC8 PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 10-20 PRRC Register 10-54 DSP56367 MOTOROLA...

  • Page 303: Port C Data Register (pdrc)

    If a port pin [i] is configured as disconnected, the corresponding PD[i] bit is not reset and contains undefined data. X:$FFFFBD PD11 PD10 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 10-21 PDRC Register MOTOROLA DSP56367 10-55...

  • Page 304: Esai Initialization Examples

    INITIALIZING JUST THE ESAI TRANSMITTER SECTION • It is assumed that the ESAI is operational; that is, at least one pin is defined as an ESAI pin. • The transmitter section should be in its personal reset state (TPR = 1). 10-56 DSP56367 MOTOROLA...

  • Page 305: Initializing Just The Esai Receiver Section

    Take the receiver section out of the personal reset state by clearing RPR. • Enable the receivers by setting their RE bits. • From now on the receivers are operating and can be serviced either by polling, interrupts, or DMA. MOTOROLA DSP56367 10-57...

  • Page 306

    Enhanced Serial Audio Interface (ESAI) ESAI Initialization Examples 10-58 DSP56367 MOTOROLA...

  • Page 307: Section 11 Enhanced Serial Audio Interface 1 (esai_1)

    The Enhanced Serial Audio Interface I (ESAI_1) is the second ESAI peripheral in the DSP56367. It is functionally identical to the ESAI peripheral described in Section 10 except for minor differences described in this section. Refer to the ESAI section for functional information about the ESAI_1, in addition to using the information in this section.

  • Page 308

    SDO3_1/SDI2_1 [PE8] (shared with SDO3/SDI2 [PC8]) SAICR_1 Shift Register SAISR_1 RX2_1 TX4_1 SDO4_1/SDI1_1 [PE7] TSR_1 Shift Register RX1_1 Clock / Frame Sync Generators TX5_1 RCLK Control Logic SDO5_1/SDI0_1 [PE6] Shift Register TCLK RX0_1 Figure 11-1 ESAI_1 Block Diagram 11-2 DSP56367 MOTOROLA...

  • Page 309: Esai_1 Data And Control Pins

    SDO3_1/SDI2_1 transmits data from the TX3_1 serial transmit shift register when programmed as a transmitter pin, or receives serial data to the RX2_1 serial receive shift register when programmed as a receiver pin. It is shared with the ESAI SDO3/SDI2 signal. MOTOROLA DSP56367 11-3...

  • Page 310: Serial Transmit 4/receive 1 Data Pin (sdo4_1/sdi1_1)

    TRANSMITTER SERIAL CLOCK (SCKT_1) SCKT_1 is a bidirectional pin that provides the transmitters serial bit clock for the ESAI_1 interface. SCKT_1 may be programmed as a general-purpose I/O pin (PE3) when the ESAI_1 SCKT_1 function is not being used. 11-4 DSP56367 MOTOROLA...

  • Page 311: Frame Sync For Receiver (fsr_1)

    The ESAI_1 also contains the GPIO Port E functionality, described in Section 11.5, “GPIO - Pins and Registers”. The following paragraphs give detailed descriptions of bits in the ESAI_1 registers that differ in functionality from their descriptions in the ESAI Programming Model. MOTOROLA DSP56367 11-5...

  • Page 312: Esai_1 Multiplex Control Register (emuxr)

    FST_1 and SCKT_1 signals. In synchronous mode, the bit clock defined for the transmitter determines the receiver bit clock as well. TCCR_1 also controls the number of words per frame for the serial data. 11-6 DSP56367 MOTOROLA...

  • Page 313: Tccr_1 Tx High Freq. Clock Divider (tfp3-tfp0) - Bits 14–17

    The ESAI_1 does not have the transmitter high frequency clock pin. THCKD must be set for proper ESAI_1 transmitter section operation. Table 11-2 Transmitter Clock Sources Transmitter THCKD TFSD TCKD OUTPUTS Bit Clock Source Reserved SCKT_1 SCKT_1 SCKT_1 FST_1 FST_1 SCKT_1 MOTOROLA DSP56367 11-7...

  • Page 314

    DIVIDE BY 1 DIVIDE BY 1 DIVIDE TO DIVIDE BY TO DIVIDE BY BY 2 DIVIDE BY 8 THCKD=1 Notes: 1. F is the DSP56300 Core internal clock frequency. Figure 11-4 ESAI_1 Clock Generator Functional Block Diagram 11-8 DSP56367 MOTOROLA...

  • Page 315

    TDC0 - TDC4 TFSL (SYNC MODE) (SYNC MODE) TFSD TX WORD CLOCK TRANSMITTER INTERNAL TX FRAME CLOCK SYNC FRAME RATE FST_1 TYPE DIVIDER TRANSMIT TRANSMIT CONTROL FRAME SYNC LOGIC Figure 11-5 ESAI_1 Frame Sync Generator Functional Block Diagram MOTOROLA DSP56367 11-9...

  • Page 316: Esai_1 Transmit Control Register (tcr_1)

    RCKP RFP3 RFP2 RFP1 RFP0 RDC4 RDC3 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 11-7 RCCR_1 Register Hardware and software reset clear all the bits of the RCCR_1 register. 11-10 DSP56367 MOTOROLA...

  • Page 317: Rccr_1 Rx High Freq. Clock Divider (rfp3-rfp0) - Bits 14–17

    REDIE REIE RFSR RFSL RSWS4 RSWS3 RSWS2 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 11-8 RCR_1 Register Hardware and software reset clear all the bits in the RCR_1 register. MOTOROLA DSP56367 11-11...

  • Page 318: Esai_1 Common Control Register (saicr_1)

    The Status Register (SAISR_1) is a read-only status register used by the DSP to read the status and serial input flags of the ESAI_1. Y:$FFFF93 RODF REDF TODE TEDE Reserved bit - read as zero; should be written with zero for future compatibility. Figure 11-10 SAISR_1 Register 11-12 DSP56367 MOTOROLA...

  • Page 319: Esai_1 Receive Shift Registers

    The unused bits (least significant portion, and the 8 most significant bits when ALC=1) of the TXx_1 are don’t care bits. The DSP is interrupted whenever the TXx_1 becomes empty if the transmit data register empty interrupt has been enabled. MOTOROLA DSP56367 11-13...

  • Page 320: Esai_1 Time Slot Register (tsr_1)

    Figure 11-11 TSMA_1 Register Y:$FFFF9A TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16 TS31 TS30 TS29 TS28 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 11-12 TSMB_1 Register 11-14 DSP56367 MOTOROLA...

  • Page 321: Receive Slot Mask Registers (rsma_1, Rsmb_1)

    Figure 11-13 RSMA_1 Register Y:$FFFF9C RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16 RS31 RS30 RS29 RS28 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 11-14 RSMB_1 Register MOTOROLA DSP56367 11-15...

  • Page 322

    Direction Register (PRRE) controls the functionality of the ESAI_1 GPIO pins. Each of the PE(11:0) bits controls the functionality of the corresponding port pin. See Table 11-4 for the port pin configurations. Hardware and software reset clear all PCRE bits. 11-16 DSP56367 MOTOROLA...

  • Page 323: Port E Direction Register (prre)

    Reserved bit - read as zero; should be written with zero for future compatibility. Figure 11-15 PCRE Register Y:$FFFF9E PDE11 PDE10 PDE9 PDE8 PDE7 PDE6 PDE4 PDE3 PDE1 PDE0 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 11-16 PRRE Register MOTOROLA DSP56367 11-17...

  • Page 324: Port E Data Register (pdre)

    If a port pin [i] is configured as disconnected, the corresponding PD[i] bit is not reset and contains undefined data. Y:$FFFF9D PD11 PD10 Reserved bit - read as zero; should be written with zero for future compatibility. Figure 11-17 PDRE Register 11-18 DSP56367 MOTOROLA...

  • Page 325: Section 12 Digital Audio Transmitter

    When the DAX interrupts are disabled, they can still be served by DMA or by a “polling” technique. A block diagram of the DAX is shown in Figure 12-1. MOTOROLA DSP56367 12-1...

  • Page 326: Dax Signals

    256 times, 384 times, or 512 times the audio sampling frequency (256 × Fs, 384 × Fs, or 512 × Fs). The ACI pin may also be used as a GPIO pin PD0 when the DAX is disabled or when operating from the internal DSP clock. MOTOROLA DSP56367 12-2...

  • Page 327: Dax Functional Overview

    XADSR are shifted out to the biphase encoder, which shifts them out through the ADO pin in the biphase mark format in the next 54 time slots. The parity generator calculates an even parity over the 27 bits of audio and non-audio data, and then outputs the result through the MOTOROLA DSP56367 12-3...

  • Page 328: Dax Programming Model

    DAX transmit underrun error XADE & XBLK VBA:$2A DAX block transferred XADE VBA:$2E DAX audio data register empty Table 12-2 DAX Interrupt Priority Priority Interrupt highest DAX transmit underrun error DAX block transferred lowest DAX audio data register empty 12-4 DSP56367 MOTOROLA...

  • Page 329: Dax Internal Architecture

    A and channel B to XADR. The XADR can be accessed with two different successive addresses. This feature supports sending non-audio data bits, channel A and channel B to the DAX in three successive DMA transfers. MOTOROLA DSP56367 12-5...

  • Page 330: Dax Audio Data Buffers (xadbufa / Xadbufb)

    The value of the XVA bit is transmitted as the twenty-ninth bit (Bit 28) of channel A subframe in the next frame. 12.5.4.2 DAX Channel A User Data (XUA)—Bit 11 The value of the XUA bit is transmitted as the thirtieth bit (Bit 29) of the channel A subframe in the next frame. 12-6 DSP56367 MOTOROLA...

  • Page 331: Dax Channel A Channel Status (xca)—bit 12

    The XCTR is a 24-bit read/write register that controls the DAX operation. The contents of the XCTR are shown in Figure 12-2. XCTR is cleared by software reset and hardware reset. The XCTR bits are described in the following paragraphs. MOTOROLA DSP56367 12-7...

  • Page 332: Audio Data Register Empty Interrupt Enable (xdie)—bit 0

    “Z” preamble and will start a new block even though the current block was not finished. This bit is cleared when the new block starts. 12.5.6.6 XCTR Reserved Bits—Bits 6-23 These XCTR bits are reserved. They read as 0 and should be written with 0 for future compatibility. 12-8 DSP56367 MOTOROLA...

  • Page 333: Dax Status Register (xstr)

    (providing the next non-audio data structures for the next block as well as storing audio data for the next frame). Writing two channels of audio data to XADR clears this bit. The relative timing of transmit frames and XADE and XBLK flags is shown in Figure 12-3. MOTOROLA DSP56367 12-9...

  • Page 334: Xstr Reserved Bits—bits 3–23

    The DAX preamble generator automatically generates one of three preambles in the 8-bit preamble shift register at the beginning of each subframe transmission, and shifts it out. The generated preambles always start with “0”. Bit patterns of preambles generated in the 12-10 DSP56367 MOTOROLA...

  • Page 335: Dax Clock Multiplexer

    (see also Section 12.5.6.4, “DAX Clock Input Select (XCS[1:0])—Bits 3–4”). The internal DSP core clock—assumes 1024 × Fs • DAX clock input pin (ACI)—512 × Fs • DAX clock input pin (ACI)—384 × Fs • DAX clock input pin (ACI)—256 × Fs • MOTOROLA DSP56367 12-11...

  • Page 336: Dax State Machine

    2. Write the non-audio data to the corresponding bits in the XNADR register 3. Write the channel A and channel B audio data in the XADR register 4. Write the transmit mode to the XCTR register 12-12 DSP56367 MOTOROLA...

  • Page 337: Audio Data Register Empty Interrupt Handling

    XADE interrupt vector will take place. 12.6.4 DAX OPERATION WITH DMA During DMA transfers, the XDIE bit of the XCTR must be cleared to avoid XADE interrupt services by the DSP core. The initialization appearing in Section 12.6.1 is relevant for DMA MOTOROLA DSP56367 12-13...

  • Page 338

    XNADR address (base address + $1) XADR address (base address + $2) DOR0 $FFFFFE; offset=-2 $FFFFFF; offset=-1 The memory organization employed for DMA transfers depends on whether or not non-audio data changes from frame to frame as shown in Figure 12-6. 12-14 DSP56367 MOTOROLA...

  • Page 339: Dax Operation During Stop

    12.7 GPIO (PORT D) - PINS AND REGISTERS The Port D GPIO functionality of the DAX is controlled by three registers: Port D Control Register (PCRD), Port D Direction Register (PRRD) and Port D Data Register (PDRD). MOTOROLA DSP56367 12-15...

  • Page 340: Port D Control Register (pcrd)

    Hardware and software reset clear all PRRD bits. Table 12-6 describes the port pin configurations. PRRD - Port D Direction Register - X:$FFFFD6 PDC1 PDC0 read as zero, should be written with zero for future compatibility Figure 12-8 Port D Direction Register (PRRD) 12-16 DSP56367 MOTOROLA...

  • Page 341: Port D Data Register (pdrd)

    PD[i] bit will reflect the value present on this pin. If a port pin [i] is configured as a GPIO output, then the value written into the corresponding PD[i] bit will be reflected on the this pin. Hardware and software reset clear all PDRD bits. MOTOROLA DSP56367 12-17...

  • Page 342

    Digital Audio Transmitter GPIO (PORT D) - Pins and Registers PDRD - Port D Data Register - X:$FFFFD5 read as zero, should be written with zero for future compatibility Figure 12-9 Port D Data Register (PDRD) 12-18 DSP56367 MOTOROLA...

  • Page 343: Section 13 Timer/ Event Counter

    This section describes the internal timer/event counter in the DSP56367. Each of the three timers (timer 0, 1 and 2) can use internal clocking to interrupt the DSP56367 or trigger DMA transfers after a specified number of events (clocks). In addition, timer 0 provides external access via the bidirectional signal TIO0.

  • Page 344: Individual Timer Block Diagram

    (TLR), a 24-bit read/write timer compare register (TCPR), and logic for clock selection and interrupt/DMA trigger generation. The timer mode is controlled by the TC[3:0] bits of the timer control/status register (TCSR). Timer modes are described in Section 13.4. 13-2 DSP56367 MOTOROLA...

  • Page 345: Timer/event Counter Programming Model

    13.3 TIMER/EVENT COUNTER PROGRAMMING MODEL The DSP56367 views each timer as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data memory space. Either standard polled or interrupt programming techniques can be used to service the timers. The timer programming model is shown in Figure 13-3.

  • Page 346

    TCPR1 = $FFFF89 TCPR2 = $FFFF85 Timer Count Register (TCR) TCR0 = $FFFF8C TCR1 = $FFFF88 TCR2 = $FFFF84 - reserved, read as 0, should be written with 0 for future compatibility Figure 13-3 Timer Module Programmer’s Model 13-4 DSP56367 MOTOROLA...

  • Page 347: Prescaler Counter

    If the prescaler source clock is external, the prescaler counter is incremented by signal transitions on the TIO0 signal. The external clock is internally synchronized to the internal clock. The external clock frequency must be lower than the DSP56367 internal operating frequency divided by 4 (CLK/4).

  • Page 348: Tplr Reserved Bit 23

    TPCR Prescaler Counter Value PC[20:0] Bits 20–0 These 21 bits contain the current value of the prescaler counter. 13.3.3.2 TPCR Reserved Bits 23–21 These reserved bits are read as zero and should be written with zero for future compatibility. 13-6 DSP56367 MOTOROLA...

  • Page 349: Timer Control/status Register (tcsr)

    Table 13-2 summarizes the TC bit functionality. A detailed description of the timer operating modes is given in Section 13.4. The TC bits are cleared by the hardware RESET signal or the software RESET instruction. MOTOROLA DSP56367 13-7...

  • Page 350

    Watchdog pulse Output Internal Watchdog toggle Output Internal Reserved — — Reserved — — Reserved — — Reserved — — Reserved — — Note: The GPIO function is enabled only if all of the TC[3:0] bits are zero. 13-8 DSP56367 MOTOROLA...

  • Page 351: Tcsr Inverter (inv) Bit 8

    Width of the low input — — pulse is measured. pulse is measured. Period is measured between Period is measured between — — the rising edges of the the falling edges of the input signal. input signal. MOTOROLA DSP56367 13-9...

  • Page 352: Tcsr Timer Reload Mode (trm) Bit 9

    The DIR bit determines the behavior of the TIO0 signal when it is used as a GPIO pin. When the DIR bit is set, the TIO0 signal is an output; when the DIR bit is cleared, the TIO0 signal is 13-10 DSP56367 MOTOROLA...

  • Page 353: Tcsr Data Input (di) Bit 12

    1 to the TOF bit. Writing a 0 to the TOF bit has no effect. The bit is also cleared when the timer overflow interrupt is serviced. The TOF bit is cleared by the hardware RESET signal, the software RESET instruction, the STOP instruction, or by clearing the TE bit to disable the timer. MOTOROLA DSP56367 13-11...

  • Page 354: Tcsr Timer Compare Flag (tcf) Bit 21

    TLR is written with a new value while the TE bit in the TCSR is set. • In all modes, if the TRM bit in the TCSR is cleared (TRM = 0), the counter operates as a free-running counter. 13-12 DSP56367 MOTOROLA...

  • Page 355: Timer Compare Register (tcpr)

    – Input width, mode 4: Input pulse width measurement – Input pulse, mode 5: Input signal period measurement – Capture, mode 6: Capture external signal • PWM, mode 7: Pulse Width Modulation • Watchdog – Pulse, mode 9: Output pulse, internal clock MOTOROLA DSP56367 13-13...

  • Page 356: Timer Modes

    TCPR. The counter is loaded with the TLR value when the first timer clock signal is received. The timer clock can be taken from either the DSP56367 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter.

  • Page 357: Timer Pulse (mode 1)

    The TIO0 signal is loaded with the value of the INV bit. The timer clock signal can be taken from either the DSP56367 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter.

  • Page 358: Timer Toggle (mode 2)

    The TIO0 signal is loaded with the value of the INV bit. The timer clock signal can be taken from either the DSP56367 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter.

  • Page 359: Timer Event Counter (mode 3)

    Timer 0 can be also be clocked from the TIO0 input signal. Each subsequent clock signal increments the counter. If an external clock is used, it must be internally synchronized to the internal clock and its frequency must be less than the DSP56367 internal operating frequency divided by 4.

  • Page 360: Measurement Accuracy

    TLR. After the first appropriate transition (as determined by the INV bit) occurs on the TIO0 input pin, the counter is loaded with the TLR value on the first timer clock signal received either from the DSP56367 clock divided by two (CLK/2) or from the prescaler clock input. Each subsequent clock signal increments the counter.

  • Page 361: Measurement Input Period (mode 5)

    After the first appropriate transition occurs on the TIO0 input pin, the counter is loaded with the TLR value on the first timer clock signal received from either the DSP56367 clock divided by two (CLK/2) or the prescaler clock output. Each subsequent clock signal increments the counter.

  • Page 362: Measurement Capture (mode 6)

    TLR. When the first timer clock signal is received, the counter is loaded with the TLR value. The timer clock signal can be taken from either the DSP56367 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter.

  • Page 363: Pulse Width Modulation (pwm, Mode 7)

    Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the TPCR. When first timer clock is received from either the DSP56367 internal clock divided by two (CLK/2) or the prescaler clock output, the counter is loaded with the TLR value.

  • Page 364: Watchdog Modes

    TCPR. The counter is loaded with the TLR value on the first timer clock received from either the DSP56367 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer clock increments the counter.

  • Page 365: Watchdog Toggle (mode 10)

    TPCR. The counter is loaded with the TLR value on the first timer clock received from either the DSP56367 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer clock increments the counter. The TIO0 signal is set to the value of the INV bit.

  • Page 366: Reserved Modes

    TIO0 signal is disconnected. Any external changes that happen to the TIO0 signal is ignored when the DSP56367 is the stop state. To ensure correct operation, the timers should be disabled before the DSP56367 is placed into the stop state.

  • Page 367: Section 14 Packaging

    Section 1 are allocated for the package. The DSP56367 is available in a 144-pin LQFP package. Table 14-1and Table 14-2 show the pin/name assignments for the packages.

  • Page 368

    SDO4/SDI1 SDO5/SDI0 GNDA SCKT VCCQH SCKR HCKT HCKR VCCQL VCCQL GNDQ GNDQ VCCQH HDS/HWR HRW/HRD GNDA HACK/HRRQ VCCA HOREQ/HTRQ VCCS GNDS GNDA TIO0 VCCA HCS/HA10 HA9/HA2 HA8/HA1 HAS/HA0 HAD7 GNDA HAD6 VCCA HAD5 Figure 14-1 144-pin package 14-2 DSP56367 MOTOROLA...

  • Page 369

    TIO0 HCKR EXTAL HCKT VCCA HCS/HA10 VCCA FSR_1 HDS/HWR VCCA HOREQ/HTRQ VCCC FST_1 HREQ# VCCC GNDA HRW/HRD VCCD GNDA MODA/IRQA# VCCD GNDA MODB/IRQB# VCCD GNDA MODC/IRQC# VCCD GNDC MODD/IRQD# VCCH GNDC MISO/SDA VCCQH CAS# GNDD MOSI/HA0 VCCQH MOTOROLA DSP56367 14-3...

  • Page 370

    Table 14-1 Signal Identification by Name (Continued) Signal Name Signal Name Signal Name Signal Name GNDD PCAP VCCQH GNDD PINIT/NMI# VCCQL GNDD VCCQL GNDH RESET# VCCQL GNDP SCK/SCL VCCQL GNDQ SCKR VCCP GNDQ SCKR_1 VCCS GNDQ SCKT VCCS GNDQ SCKT_1 14-4 DSP56367 MOTOROLA...

  • Page 371

    VCCQL GNDQ EXTAL VCCQL GNDQ VCCQH VCCQL HDS/HWR VCCC VCCD HRW/HRD GNDC GNDD HACK/HRRQ FSR_1 VCCQH HOREQ/HTRQ SCKR_1 GNDA VCCS PINIT/NMI# GNDS MODD/IRQD# MODC/IRQC# MODB/IRQB# TIO0 VCCC MODA/IRQA# HCS/HA10 GNDC SDO4_1/SDI1_1 HA9/HA2 VCCD HA8/HA1 GNDD HAS/HA0 HAD7 MOTOROLA DSP56367 14-5...

  • Page 372

    Packaging Pin-out and Package Information Table 14-2 Signal Identification by Pin Number (Continued) HAD6 MOSI/HA0 HAD5 MISO/SDA 14-6 DSP56367 MOTOROLA...

  • Page 373: Lqfp Package Mechanical Drawing

    Packaging Pin-out and Package Information 14.1.2 LQFP PACKAGE MECHANICAL DRAWING Figure 14-2 DSP56367 144-pin LQFP Package MOTOROLA DSP56367 14-7...

  • Page 374: Ordering Drawings

    Packaging Ordering Drawings 14.2 ORDERING DRAWINGS The detailed package drawing is available on the Motorola web page at: http://www.mot-sps.com/cgi-bin/cases.pl Use package 918-03 for the search. 14-8 DSP56367 MOTOROLA...

  • Page 375: A.1 Dsp56367 Bootstrap Program

    0110. - Added 5 NOP instructions after OnCE enable. ; This is the Bootstrap program contained in the DSP56367 192-word Boot ; ROM. This program can load any program RAM segment from an external ; EPROM, from the Host Interface or from the SHI serial interface.

  • Page 376

    ; After reading the program words, program execution starts from the same ; address where loading started. ; The Host Interface bootstrap load program may be stopped by ; setting the Host Flag 0 (HF0). This will start execution of the loaded ; program from the specified starting address. DSP56367 MOTOROLA...

  • Page 377

    ;;;;;;;;;;;;;;;;;;;; GENERAL EQUATES ;;;;;;;;;;;;;;;;;;;;;;;; BOOT $D00000 ; this is the location in P memory ; on the external memory bus ; where the external byte-wide ; EPROM is located AARV $D00409 ; AAR1 selects the EPROM as CE~ MOTOROLA DSP56367...

  • Page 378

    ; If MD:MC:MB:MA=01xx, go load from SHI jclr #MB,omr,EPROMLD ; If MD:MC:MB:MA=0001, go load from EPROM jset #MA,omr,RESERVED ; If MD:MC:MB:MA=0011, go to RESERVED ;======================================================================== ; This is the routine that jumps to the internal Program ROM. ; MD:MC:MB:MA=0010 DSP56367 MOTOROLA...

  • Page 379

    ; wait for no. of words movep x:M_HRX,a0 jclr #HRNE,x:M_HCSR,* ; wait for starting address movep x:M_HRX,r0 move r0,r1 a0,_LOOP2 jclr #HRNE,x:M_HCSR,* ; wait for HRX not empty movep x:M_HRX,p:(r0)+ ; store in Program RAM ; req. because of restriction _LOOP2 MOTOROLA DSP56367...

  • Page 380

    ; The program is downloaded from the host MCU with the following rules: ; 1) 3 bytes - Define the program length. ; 2) 3 bytes - Define the address to which to start loading the program to. DSP56367 MOTOROLA...

  • Page 381

    ; HA8EN = 0 (address 8 enable bit has no meaning in non-multiplexed bus) ; HGEN = 0 Host GPIO pins are disabled <HDI08CONT OMR1IS0 jset #MA,omr,HC11HOSTLD ; If MD:MC:MB:MA=1101, go load from HC11 Host MOTOROLA DSP56367...

  • Page 382

    HEN should be cleared ; HAEN = 0 Host acknowledge is disabled ; HREN = 1 Host requests are enabled ; HCSEN = 1 Host chip select input enabled ; HA9EN = 0 (address 9 enable bit has no DSP56367 MOTOROLA...

  • Page 383

    ; set a loop with the downloaded length HDI08LL jset #HRDF,x:M_HSR,HDI08NW ; If new word was loaded then jump to ; read that word jclr #HF0,x:M_HSR,HDI08LL ; If HF0=0 then continue with the MOTOROLA DSP56367...

  • Page 384

    ;; Port C GPIO Data Register M_PRRC $FFFFBE ;; Port C Direction Register SCKT ;; SCKT is GPIO bit #3 in ESAI (Port C) EQUALDATA ;; 1 if xram and yram are of equal ;; size and addresses, 0 otherwise. (EQUALDATA) A-10 DSP56367 MOTOROLA...

  • Page 385

    ;; exercise mac, write x/y ram else ;; x/y ram not symmetrical ;; write x memory clr a #start_xram,r0 ;; start of xram move #>length_xram,n0 ;; length of xram mac x0,y0,a x1,x:(r0)+ ;; exercise mac, write xram MOTOROLA DSP56367 A-11...

  • Page 386

    _loopx ;; check yram clr a #start_yram,r1 ;; restore pointer, clear a n1,_loopy move y:(r1)+,a1 ;; a0=a2=0 x0,a ;; accumulate error in b _loopy endif ;; check pram clr a #start_pram,r2 ;; restore pointer, clear a n2,_loopp A-12 DSP56367 MOTOROLA...

  • Page 387

    BURN_END ORG PL:,PL: PATTERNS ;; align for correct modulo addressing PL:BURN_END,PL:BURN_END dup PATTERNS-* ; write address in unused Boot ROM location dc * endm PL:PATTERNS,PL:PATTERNS ;; Each value is written to all memories $555555 $AAAAAA $333333 $F0F0F0 MOTOROLA DSP56367 A-13...

  • Page 388

    #$80000,r0 move #$0,x0 move x0,x:(r0)+ move #$1,x0 move x0,x:(r0)+ move #$2,x0 move x0,x:(r0)+ move #$3,x0 move x0,x:(r0)+ move #$4,x0 move x0,x:(r0)+ move #$5,x0 move x0,x:(r0)+ move #$6,x0 move x0,x:(r0)+ move #$7,x0 move x0,x:(r0)+ move #$8,x0 move x0,x:(r0)+ A-14 DSP56367 MOTOROLA...

  • Page 389

    Bootstrap ROM Contents MOTOROLA DSP56367 A-15...

  • Page 390

    Bootstrap ROM Contents A-16 DSP56367 MOTOROLA...

  • Page 391

    APPENDIX EQUATES ;********************************************************************************* EQUATES for DSP56367 interrupts Last update: April 24, 2000 ;********************************************************************************* page 132,55,0,0,0 intequ ident @DEF(I_VEC) ;leave user definition as is. else I_VEC endif ;------------------------------------------------------------------------ ; Non-Maskable interrupts ;------------------------------------------------------------------------ I_RESET EQU I_VEC+$00 ; Hardware RESET I_STACK EQU I_VEC+$02 ;...

  • Page 392

    I_DMA5 I_VEC+$22 ; DMA Channel 5 ;------------------------------------------------------------------------ ; DAX Interrupts ;------------------------------------------------------------------------ I_DAXTUE EQU I_VEC+$28 ; DAX Underrun Error I_DAXBLK EQU I_VEC+$2A ; DAX Block Transferred I_DAXTD EQU I_VEC+$2E ; DAX Audio Data Empty ;------------------------------------------------------------------------ ; ESAI Interrupts ;------------------------------------------------------------------------ DSP56367 MOTOROLA...

  • Page 393

    ; TIMER 0 compare I_TIM0OF EQU I_VEC+$56 ; TIMER 0 overflow I_TIM1C EQU I_VEC+$58 ; TIMER 1 compare I_TIM1OF EQU I_VEC+$5A ; TIMER 1 overflow I_TIM2C EQU I_VEC+$5C ; TIMER 2 compare I_TIM2OF EQU I_VEC+$5E ; TIMER 2 overflow ;------------------------------------------------------------------------ MOTOROLA DSP56367...

  • Page 394

    ; ESAI_1 Transmit Last Slot ;------------------------------------------------------------------------ ; INTERRUPT ENDING ADDRESS ;------------------------------------------------------------------------ I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space ;------------------ end of intequ.asm ------------------------ ;********************************************************************************* EQUATES for DSP56367 I/O registers and ports Last update: April 24, 2000 ;********************************************************************************* DSP56367 MOTOROLA...

  • Page 395

    ; Port D GPIO Data Register M_PCRE $FFFFD7 ; Port E Control register M_PRRE $FFFFD6 ; Port E Direction Data Register M_PDRE $FFFFD5 ; Port E GPIO Data Register M_OGDB $FFFFFC ; OnCE GDB Register ;------------------------------------------------------------------------ EQUATES for Exception Processing ;------------------------------------------------------------------------ MOTOROLA DSP56367...

  • Page 396

    ; DMA0 Interrupt Priority Level (low) M_D0L1 ; DMA0 Interrupt Priority Level (high) M_D1L $C000 ; DMA1 Interrupt Priority Level Mask M_D1L0 ; DMA1 Interrupt Priority Level (low) M_D1L1 ; DMA1 Interrupt Priority Level (high) M_D2L $30000 ; DMA2 Interrupt priority Level Mask DSP56367 MOTOROLA...

  • Page 397

    ; HDI08 Interrupt Priority Level (high) M_DAL ; DAX Interrupt Priority Level Mask M_DAL0 ; DAX Interrupt Priority Level (low) M_DAL1 ; DAX Interrupt Priority Level (high) M_TAL $300 ;Timer Interrupt Priority Level Mask M_TAL0 ;Timer Interrupt Priority Level (low) MOTOROLA DSP56367...

  • Page 398

    Register Addresses Of DMA1 M_DSR1 $FFFFEB ; DMA1 Source Address Register M_DDR1 $FFFFEA ; DMA1 Destination Address Register M_DCO1 $FFFFE9 ; DMA1 Counter M_DCR1 $FFFFE8 ; DMA1 Control Register Register Addresses Of DMA2 M_DSR2 $FFFFE7 ; DMA2 Source Address Register DSP56367 MOTOROLA...

  • Page 399

    ; DMA Source Space Mask (DSS0-Dss1) M_DSS0 ; DMA Source Memory space 0 M_DSS1 ; DMA Source Memory space 1 M_DDS ; DMA Destination Space Mask (DDS-DDS1) M_DDS0 ; DMA Destination Memory Space 0 M_DDS1 ; DMA Destination Memory Space 1 MOTOROLA DSP56367...

  • Page 400

    M_DTM2 ; DMA Transfer Mode 2 M_DIE ; DMA Interrupt Enable bit M_DE ; DMA Channel Enable bit DMA Status Register M_DTD ; Channel Transfer Done Status MASK (DTD0-DTD5) M_DTD0 ; DMA Channel Transfer Done Status 0 B-10 DSP56367 MOTOROLA...

  • Page 401

    ; Multiplication Factor Bits Mask (MF0-MF11) M_MF0 ;Multiplication Factor bit 0 M_MF1 ;Multiplication Factor bit 1 M_MF2 ;Multiplication Factor bit 2 M_MF3 ;Multiplication Factor bit 3 M_MF4 ;Multiplication Factor bit 4 M_MF5 ;Multiplication Factor bit 5 M_MF6 ;Multiplication Factor bit 6 MOTOROLA DSP56367 B-11...

  • Page 402

    ;PreDivider Factor bit 0 M_PD1 ;PreDivider Factor bit 1 M_PD2 ;PreDivider Factor bit 2 M_PD3 ;PreDivider Factor bit 3 ;------------------------------------------------------------------------ EQUATES for BIU ;------------------------------------------------------------------------ Register Addresses Of BIU M_BCR $FFFFFB ; Bus Control Register M_DCR $FFFFFA ; DRAM Control Register B-12 DSP56367 MOTOROLA...

  • Page 403

    M_BA2W2 ;Area 2 Wait Control Bit 2 M_BA3W $E000 ; Area 3 Wait Control Mask (BA3W0-BA3W3) M_BA3W0 ;Area 3 Wait Control Bit 0 M_BA3W1 ;Area 3 Wait Control Bit 1 M_BA3W2 ;Area 3 Wait Control Bit 2 MOTOROLA DSP56367 B-13...

  • Page 404

    ; Mastership Enable M_BRE ; Refresh Enable M_BSTR ; Software Triggered Refresh M_BRF $7F8000 ; Refresh Rate Bits Mask (BRF0-BRF7) M_BRF0 ; Refresh Rate Bit 0 M_BRF1 ; Refresh Rate Bit 1 M_BRF2 ; Refresh Rate Bit 2 B-14 DSP56367 MOTOROLA...

  • Page 405

    M_BAC $FFF000 ; Address to Compare Bits Mask (BAC0-BAC11) M_BAC0 ; Address to Compare Bits 0 M_BAC1 ; Address to Compare Bits 1 M_BAC2 ; Address to Compare Bits 2 M_BAC3 ; Address to Compare Bits 3 MOTOROLA DSP56367 B-15...

  • Page 406

    ; Interupt Mask Bit 1 M_S0 ; Scaling Mode Bit 0 M_S1 ; Scaling Mode Bit 1 M_SC ; Sixteen_Bit Compatibility M_DM ; Double Precision Multiply M_LF ; DO-Loop Flag M_FV ; DO-Forever Flag M_SA ; Sixteen-Bit Arithmetic B-16 DSP56367 MOTOROLA...

  • Page 407

    ;Addess Priority Disable M_ATE ;Address Tracing Enable M_XYS ; Stack Extension space select bit in OMR. M_EUN ; Extensed stack UNderflow flag in OMR. M_EOV ; Extended stack OVerflow flag in OMR. M_WRP ; Extended WRaP flag in OMR. MOTOROLA DSP56367 B-17...

  • Page 408

    ; DAX Channel A User Data (XUA) M_XCA ; DAX Channel A Channel Status (XCA) M_XVB ; DAX Channel B Validity (XVB) M_XUB ; DAX Channel B User Data (XUB) M_XCB ; DAX Channel B Channel Status (XCB) B-18 DSP56367 MOTOROLA...

  • Page 409

    ; SHI I2C Slave Address (HA5) M_HA4 ; SHI I2C Slave Address (HA4) M_HA3 ; SHI I2C Slave Address (HA3) M_HA1 ; SHI I2C Slave Address (HA1) control and status bits in HCSR M_HBUSY EQU ; SHI Host Busy (HBUSY) MOTOROLA DSP56367 B-19...

  • Page 410

    HCKR M_HFM1 ; SHI Filter Model (HFM1) M_HFM0 ; SHI Filter Model (HFM0) M_HDM7 ; SHI Divider Modulus Select (HDM7) M_HDM6 ; SHI Divider Modulus Select (HDM6) M_HDM5 ; SHI Divider Modulus Select (HDM5) B-20 DSP56367 MOTOROLA...

  • Page 411

    ; ESAI_1 Transmit Clock Control Register (TCCR_1) M_TCR_1 EQU $FFFF95 ; ESAI_1 Transmit Control Register (TCR_1) M_SAICR_1 EQU $FFFF94 ; ESAI_1 Control Register (SAICR_1) M_SAISR_1 EQU $FFFF93 ; ESAI_1 Status Register (SAISR_1) M_RX3_1 EQU $FFFF8B ; ESAI_1 Receive Data Register 3 (RX3_1) MOTOROLA DSP56367 B-21...

  • Page 412

    ; ESAI Receive Clock Control Register (RCCR) M_RCR $FFFFB7 ; ESAI Receive Control Register (RCR) M_TCCR $FFFFB6 ; ESAI Transmit Clock Control Register (TCCR) M_TCR $FFFFB5 ; ESAI Transmit Control Register (TCR) M_SAICR EQU $FFFFB4 ; ESAI Control Register (SAICR) B-22 DSP56367 MOTOROLA...

  • Page 413

    ; ESAI M_RS29 ; ESAI M_RS28 ; ESAI M_RS27 ; ESAI M_RS26 ; ESAI M_RS25 ; ESAI M_RS24 ; ESAI M_RS23 ; ESAI M_RS22 ; ESAI M_RS21 ; ESAI M_RS20 ; ESAI M_RS19 ; ESAI M_RS18 ; ESAI MOTOROLA DSP56367 B-23...

  • Page 414

    ; ESAI M_RS4 ; ESAI M_RS3 ; ESAI M_RS2 ; ESAI M_RS1 ; ESAI M_RS0 ; ESAI TSMB Register bits M_TS31 ; ESAI M_TS30 ; ESAI M_TS29 ; ESAI M_TS28 ; ESAI M_TS27 ; ESAI M_TS26 ; ESAI B-24 DSP56367 MOTOROLA...

  • Page 415

    ; ESAI M_TS11 ; ESAI M_TS10 ; ESAI M_TS9 ; ESAI M_TS8 ; ESAI M_TS7 ; ESAI M_TS6 ; ESAI M_TS5 ; ESAI M_TS4 ; ESAI M_TS3 ; ESAI M_TS2 ; ESAI M_TS1 ; ESAI M_TS0 ; ESAI MOTOROLA DSP56367 B-25...

  • Page 416

    M_RDC4 ; ESAI M_RDC3 ; ESAI M_RDC2 ; ESAI M_RDC1 ; ESAI M_RDC0 ; ESAI M_RPSR ; ESAI M_RPM M_RPM7 ; ESAI M_RPM6 ; ESAI M_RPM5 ; ESAI M_RPM4 ; ESAI M_RPM3 ; ESAI M_RPM2 ; ESAI B-26 DSP56367 MOTOROLA...

  • Page 417

    ; ESAI M_RSWS0 ; ESAI M_RMOD $300 M_RMOD1 EQU ; ESAI M_RMOD0 EQU ; ESAI M_RWA ; ESAI M_RSHFD EQU ; ESAI M_RE M_RE3 ; ESAI M_RE2 ; ESAI M_RE1 ; ESAI M_RE0 ; ESAI TCCR Register bits MOTOROLA DSP56367 B-27...

  • Page 418

    M_TDC3 ; ESAI M_TDC2 ; ESAI M_TDC1 ; ESAI M_TDC0 ; ESAI M_TPSR ; ESAI M_TPM M_TPM7 ; ESAI M_TPM6 ; ESAI M_TPM5 ; ESAI M_TPM4 ; ESAI M_TPM3 ; ESAI M_TPM2 ; ESAI M_TPM1 ; ESAI B-28 DSP56367 MOTOROLA...

  • Page 419

    ; ESAI M_TSWS0 ; ESAI M_TMOD $300 M_TMOD1 EQU ; ESAI M_TMOD0 EQU ; ESAI M_TWA ; ESAI M_TSHFD EQU ; ESAI M_TEM M_TE5 ; ESAI M_TE4 ; ESAI M_TE3 ; ESAI M_TE2 ; ESAI M_TE1 ; ESAI MOTOROLA DSP56367 B-29...

  • Page 420

    M_TDE ; ESAI M_TUE ; ESAI M_TFS ; ESAI M_RODF ; ESAI M_REDF ; ESAI M_RDF ; ESAI M_ROE ; ESAI M_RFS ; ESAI M_IF2 ; ESAI M_IF1 ; ESAI M_IF0 ; ESAI ;------------------------------------------------------------------------ EQUATES for HDI08 B-30 DSP56367 MOTOROLA...

  • Page 421

    ; HOST DMA Mode Control Bit 2 HSR bits M_HRDF ; HOST Receive Data Full M_HOTDE ; HOST Receive Data Emptiy M_HCP ; HOST Command Pending M_HF0 ; HOST Flag 0 M_HF1 ; HOST Flag 1 M_DMA ; HOST DMA Status MOTOROLA DSP56367 B-31...

  • Page 422

    ; HOST Multiplexed bus select M_HDDS ; HOST Double/Single Strobe select M_HCSP ; HOST Chip Select Polarity M_HRP ; HOST Request Polarity M_HAP ; HOST Acknowledge Polarity HBAR BITS M_BA M_BA10 M_BA9 M_BA8 M_BA7 M_BA6 M_BA5 M_BA4 M_BA3 B-32 DSP56367 MOTOROLA...

  • Page 423

    ; TIMER Prescaler Load Register M_TPCR $FFFF82 ; TIMER Prescalar Count Register Timer Control/Status Register Bit Flags M_TE ; Timer Enable M_TOIE ; Timer Overflow Interrupt Enable M_TCIE ; Timer Compare Interrupt Enable M_TC ; Timer Control Mask (TC0-TC3) MOTOROLA DSP56367 B-33...

  • Page 424

    ; Prescaler Source Mask M_PS0 EQU 21 M_PS1 EQU 22 Timer Control Bits M_TC0 ; Timer Control 0 M_TC1 ; Timer Control 1 M_TC2 ; Timer Control 2 M_TC3 ; Timer Control 3 ;------------------ end of ioequ.asm ------------------------ B-34 DSP56367 MOTOROLA...

  • Page 425

    S S D T J T A G S O F T W A R E -- BSDL File Generated: Mon Jan 18 10:13:53 1999 -- Revision History: entity DSP56367 is generic (PHYSICAL_PIN_MAP : string := "TQFP144"); port ( TDO:out bit;...

  • Page 426

    FSR_1:inout bit; SCKR_1:inout bit; SCKT_1:inout bit); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of DSP56367 : entity is "STD_1149_1_1993"; attribute PIN_MAP of DSP56367 : entity is PHYSICAL_PIN_MAP; constant TQFP144 : PIN_MAP_STRING := "SCK: 1, " & "SS_: 2, " & "HREQ_: 3, " &...

  • Page 427

    134, " & "MODC: 135, " & "MODB: 136, " & "MODA: 137, " & "SDO41_1: 138, " & "TDO: 139, " & "TDI: 140, " & "TCK: 141, " & "TMS: 142, " & "MOSI: 143, " & MOTOROLA DSP56367...

  • Page 428

    TDO : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH); attribute INSTRUCTION_LENGTH of DSP56367 : entity is 4; attribute INSTRUCTION_OPCODE of DSP56367 : entity is "EXTEST (0000)," &...

  • Page 429

    X)," & "62 (BC_1, TA_, input, X)," & "63 (BC_1, PINIT, input, X)," & "64 (BC_1, *, control, 1)," & "65 (BC_6, SCKR_1, bidir, Z)," & "66 (BC_1, *, control, 1)," & "67 (BC_6, FSR_1, bidir, Z)," & MOTOROLA DSP56367...

  • Page 430

    (BC_1, *, control, 1)," & "114 (BC_6, HP(15), bidir, 113, Z)," & "115 (BC_1, *, control, 1)," & "116 (BC_6, HP(11), bidir, 115, Z)," & "117 (BC_1, *, control, 1)," & "118 (BC_6, HP(12), bidir, 117, Z)," & DSP56367 MOTOROLA...

  • Page 431

    (BC_1, *, control, 1)," & "147 (BC_6, SCK, bidir, 146, Z)," & "148 (BC_1, *, control, 1)," & "149 (BC_6, SDA, bidir, 148, Z)," & "150 (BC_1, *, control, 1)," & "151 (BC_6, MOSI, bidir, 150, Z)"; end DSP56367; MOTOROLA DSP56367...

  • Page 432

    JTAG BSDL DSP56367 MOTOROLA...

  • Page 433: D.1 Introduction

    Table D-3 D.1.4 Host Interface Quick Reference is a quick reference guide to the host interface (HDI08). Table D-4 D.1.5 Programming Sheets The remaining figures describe major programmable registers on the DSP56367. MOTOROLA DSP56367...

  • Page 434: D.2 Internal I/o Memory Map

    DMA SOURCE ADDRESS REGISTER (DSR5) X:$FFFFDA DMA DESTINATION ADDRESS REGISTER (DDR5) X:$FFFFD9 DMA COUNTER (DCO5) X:$FFFFD8 DMA CONTROL REGISTER (DCR5) PORT D X:$FFFFD7 PORT D CONTROL REGISTER (PCRD) X:$FFFFD6 PORT D DIRECTION REGISTER (PRRD) X:$FFFFD5 PORT D DATA REGISTER (PDRD) DSP56367 MOTOROLA...

  • Page 435

    HOST PORT CONTROL REGISTER (HPCR) X:$FFFFC3 HOST STATUS REGISTER (HSR) X:$FFFFC2 HOST CONTROL REGISTER (HCR) X:$FFFFC1 RESERVED X:$FFFFC0 RESERVED PORT C X:$FFFFBF PORT C CONTROL REGISTER (PCRC) X:$FFFFBE PORT C DIRECTION REGISTER (PRRC) X:$FFFFBD PORT C GPIO DATA REGISTER (PDRC) MOTOROLA DSP56367...

  • Page 436

    RESERVED X:$FFFF98 RESERVED X:$FFFF97 RESERVED X:$FFFF96 RESERVED X:$FFFF95 RESERVED X:$FFFF94 SHI RECEIVE FIFO (HRX) X:$FFFF93 SHI TRANSMIT REGISTER (HTX) X:$FFFF92 SHI I C SLAVE ADDRESS REGISTER (HSAR) X:$FFFF91 SHI CONTROL/STATUS REGISTER (HCSR) X:$FFFF90 SHI CLOCK CONTROL REGISTER (HCKR) DSP56367 MOTOROLA...

  • Page 437

    RESERVED Y:$FFFFA8 RESERVED Y:$FFFFA7 RESERVED Y:$FFFFA6 RESERVED Y:$FFFFA5 RESERVED Y:$FFFFA4 RESERVED Y:$FFFFA3 RESERVED Y:$FFFFA2 RESERVED Y:$FFFFA1 RESERVED Y:$FFFFA0 RESERVED PORT E Y:$FFFF9F PORT E CONTROL REGISTER (PCRE) Y:$FFFF9E PORT E DIRECTION REGISTER(PRRE) Y:$FFFF9D PORT E GPIO DATA REGISTER(PDRE) MOTOROLA DSP56367...

  • Page 438

    ESAI_1 TRANSMIT DATA REGISTER 5 (TX5_1) Y:$FFFF84 ESAI_1 TRANSMIT DATA REGISTER 4 (TX4_1) Y:$FFFF83 ESAI_1 TRANSMIT DATA REGISTER 3 (TX3_1) Y:$FFFF82 ESAI_1 TRANSMIT DATA REGISTER 2 (TX2_1) Y:$FFFF81 ESAI_1 TRANSMIT DATA REGISTER 1 (TX1_1) Y:$FFFF80 ESAI_1 TRANSMIT DATA REGISTER 0 (TX0_1) DSP56367 MOTOROLA...

  • Page 439: D.3 Interrupt Vector Addresses

    Programmer’s Reference INTERRUPT VECTOR ADDRESSES Table D-2 DSP56367 Interrupt Vectors Interrupt Interrupt Priority Interrupt Source Starting Address Level Range VBA:$00 Hardware RESET VBA:$02 Stack Error VBA:$04 Illegal Instruction VBA:$06 Debug Request Interrupt VBA:$08 Trap VBA:$0A Non-Maskable Interrupt (NMI) VBA:$0C Reserved For Future Level-3 Interrupt Source...

  • Page 440

    Programmer’s Reference Table D-2 DSP56367 Interrupt Vectors (Continued) Interrupt Interrupt Priority Interrupt Source Starting Address Level Range VBA:$3E 0 - 2 ESAI Transmit Last Slot VBA:$40 0 - 2 SHI Transmit Data VBA:$42 0 - 2 SHI Transmit Underrun Error...

  • Page 441

    Programmer’s Reference Table D-2 DSP56367 Interrupt Vectors (Continued) Interrupt Interrupt Priority Interrupt Source Starting Address Level Range VBA:$80 0 - 2 Reserved VBA:$FE 0 - 2 Reserved MOTOROLA DSP56367...

  • Page 442: D.4 Interrupt Source Priorities (within An Ipl)

    ESAI Transmit Last Slot ESAI Transmit Even Data ESAI Transmit Data SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty HOST Command Interrupt D-10 DSP56367 MOTOROLA...

  • Page 443

    TIMER2 Compare Interrupt ESAI_1 Receive Data with Exception Status ESAI_1 Receive Even Data ESAI_1 Receive Data ESAI_1 Receive Last Slot ESAI_1 Transmit Data with Exception Status ESAI_1 Transmit Last Slot ESAI_1 Transmit Even Data Lowest ESAI_1 Transmit Data MOTOROLA DSP56367 D-11...

  • Page 444: D.5 Host Interface—quick Reference

    Host Flag 3 HDM[2:0] Host DMA Mode DMA operation disabled DMA operation enabled 24-bit host-to-DSP DMA enabled 16-bit host-to-DSP DMA enabled 8-bit host-to-DSP DMA enabled 24-bit DSP-to-host DMA enabled 16-bit DSP-to-host DMA enabled 8-bit DSP-to-host DMA enabled D-12 DSP56367 MOTOROLA...

  • Page 445

    Empty transmit data reg. not empty Host Command Pending no host command pending host command pending Host Flag0 Host Flag1 DMA Status DMA mode disabled DMA mode enabled HBAR 7-0 BA10-BA3 Host base Address Register MOTOROLA DSP56367 D-13...

  • Page 446

    HDI08 host command pending hardware when the HC int. req. is serviced RXH/ Host Receive Data empty Register TXH/ Host Transmit Data empty Register IV7-IV0 Interrupt Register 68000 family vector register D-14 DSP56367 MOTOROLA...

  • Page 447: D.6 Programming Sheets

    Programmer’s Reference PROGRAMMING SHEETS The worksheets shown on the following pages contain listings of major programmable registers for the DSP56367. The programming sheets are grouped into the following order: • Central Processor • Host Interface (HDI08) • Serial Host Interface (SHI) •...

  • Page 448

    15 14 13 12 11 10 CP1 CP0 RM Extended Mode Register (MR) Mode Register (MR) Condition Code Register (CCR) = Reserved, Program as 0 Status Register (SR) Read/Write Reset = $C00300 Figure D-1 Status Register (SR) D-16 DSP56367 MOTOROLA...

  • Page 449

    MSW1 MSW0 System Stack Control Extended Chip Operating Chip Operating Mode Status Register (SCS) Mode Register (COM) Register (COM) Operating Mode Register (OMR) Read/Write Reset = $00030X = Reserved, Program as 0 Figure D-2 Operating Mode Register (OMR) MOTOROLA DSP56367 D-17...

  • Page 450

    CENTRAL PROCESSOR IRQC Mode IRQA Mode ICL2 Trigger ICL1 ICL0 Enabled IAL2 Trigger IAL1 IAL0 Enabled Level — Level — Neg. Edge Neg. Edge IRQD Mode IRQB Mode IDL1 IDL0 Enabled IDL2 Trigger IBL2 Trigger IBL1 IBL0 Enabled — Level Level —...

  • Page 451

    CENTRAL PROCESSOR ESAI IPL HDI08 IPL ESAI_1 IPL ESL1 ESL0 Enabled HDL1 HDL0 Enabled ESL1 ESL0 Enabled — — — TEC IPL DAX IPL SHI IPL SHL1 SHL0 Enabled TAL1 TAL0 Enabled DAL1 DAL0 Enabled — — — 23 22 21 20 19 18 15 14 13 12 11 10 ESL11 TAL1...

  • Page 452

    Programmer’s Reference Date: Application: Programmer: Sheet 5 of 5 Figure D-5 Phase Lock Loop Control Register (PCTL) D-20 DSP56367 MOTOROLA...

  • Page 453

    19 18 17 16 15 14 13 12 11 10 Transmit High Byte Transmit Middle Byte Transmit Low Byte Host Transmit Register (HOTX) X:$FFFEC7 Write Only Reset = empty Figure D-6 Host Receive and Host Transmit Data Registers MOTOROLA DSP56367 D-21...

  • Page 454

    Host Flags Read Only DMA status 0 = DMA Mode Disabled HTDE HRDF 1 = DMA Mode Enabled Host Status Register (HSR) X:$FFFFC3 Reset = $2 = Reserved, Program as 0 Figure D-7 Host Control and Status Registers D-22 DSP56367 MOTOROLA...

  • Page 455

    0 = HACK Active Low, 1 = HACK Active High HCSP HDDS HMUX HASP HDSP HROD HAEN HREN HCSEN HA9EN HA8EN HGEN Host Port Control Register (HPCR) X:$FFFFC4 Read/Write Reset = $0 = Reserved, Program as 0 Figure D-8 Host Base Address and Host Port Control MOTOROLA DSP56367 D-23...

  • Page 456

    Read Only Host Request 0 = HOREQ Deasserted 1 = HOREQ Asserted HREQ TRDY TXDE RXDF Interrupt Status Register (ISR) $2 R/W Reset = $0 = Reserved, Program as 0 Figure D-9 Host Interrupt Control and Interrupt Status D-24 DSP56367 MOTOROLA...

  • Page 457

    Contains Host Command Interrupt Address ÷ 2 Host Command Handshakes Executing Host Command Interrupts Command Vector Register (CVR) $1 R/W Reset = $32 Contains the host command interrupt address Figure D-10 Host Interrupt Vector and Command Vector MOTOROLA DSP56367 D-25...

  • Page 458

    Host Transmit Data (HLEND = 1) Transmit Low Byte Transmit Middle Byte Transmit High Byte Not Used Transmit Byte Registers Transmit Byte Registers $7, $6, $5, $4 Write Only Reset = Empty Figure D-11 Host Receive and Transmit Byte Registers D-26 DSP56367 MOTOROLA...

  • Page 459

    HSAR I C Slave Address Slave address = Bits HA6-HA3, HA1 and external pins HA2, HA0 Slave address after reset = 1011[HA2]0[HA0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SHI Slave Address Register (HSAR) X:$FFFF92 Reset = $Bx0000 SHI Slave Address Register (HSAR)

  • Page 460

    Host Transmit Data Register 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SHI Host Transmit Data Register (HTX) X:$FFFF93 Write Only Reset = $xxxxxx SHI Host Transmit Data Register (HTX) Host Receive Data Register 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

  • Page 461

    Programmer’s Reference Date: Application: Programmer: Sheet 3 of 3 Figure D-14 SHI Host Control/Status Register MOTOROLA DSP56367 D-29...

  • Page 462

    Programmer’s Reference Date: Application: Programmer: Figure D-15 ESAI Transmit Clock Control Register D-30 DSP56367 MOTOROLA...

  • Page 463

    Programmer’s Reference Date: Application: Programmer: Figure D-16 ESAI Transmit Control Register MOTOROLA DSP56367 D-31...

  • Page 464

    RCCR - ESAI Receive Clock Control Register Description RHCKD ESAI X: $FFFFB8 Reset: $000000 HCKR is input HCKR is output Description RFSD FSR is input FSR is output Description RCKD RFP [3:0] Description External clock source used Sets divide rate for receiver high frequency clock Range $0 - $F (1 -16).

  • Page 465

    RCR - ESAI Receive Control Register ESAI RLIE Description X: $FFFFB7 Reset: $000000 Receive Last Slot Interrupt disabled Receive Last Slot interrupt enabled RFSL Description Word length frame sync Description 1-bit clock period frame sync Receive Interrupt disabled Receive interrupt enabled RSWS [0:4] Description Defines slot and data word length...

  • Page 466

    Programmer’s Reference Date: Application: Programmer: Figure D-19 ESAI Common Control Register D-34 DSP56367 MOTOROLA...

  • Page 467

    SAISR - ESAI Status Register ESAI X: $FFFFB3 Reset $000000 RODF Description Description Receive odd-data register empty REDF Receive odd-data register full Receive even-data register empty Receive even-data register full Description Reserved Description Receive data register empty Description Receive data register full Transmit Frame sync did not occur during word transmission Transmit frame sync occurred during word transmission Description...

  • Page 468

    Programmer’s Reference Date: Application: Programmer: Figure D-21 ESAI_1 Multiplex Control Register D-36 DSP56367 MOTOROLA...

  • Page 469

    Programmer’s Reference Date: Application: Programmer: Figure D-22 ESAI_1 Transmit Clock Control Register MOTOROLA DSP56367 D-37...

  • Page 470

    Programmer’s Reference Date: Application: Programmer: Figure D-23 ESAI_1 Transmit Control Register D-38 DSP56367 MOTOROLA...

  • Page 471

    RCCR_1 - ESAI_1 Receive Clock Control Register Description RHCKD Y: $FFFF98 Reset: $000000 Reserved ESAI_1 Must be set for proper operation Description RFSD FSR_1 is input FSR_1 is output Description RCKD RFP [3:0] Description External clock source used Sets divide rate Range $0 - $F (1 -16).

  • Page 472

    RCR_1 - ESAI_1 Receive Control Register ESAI_1 RLIE Description Y: $FFFF97 Reset: $000000 Receive Last Slot Interrupt disabled Receive Last Slot interrupt enabled RFSL Description Word length frame sync Description 1-bit clock period frame sync Receive Interrupt disabled Receive interrupt enabled RSWS [0:4] Description Defines slot and data word length...

  • Page 473

    Programmer’s Reference Date: Application: Programmer: Figure D-26 ESAI_1 Common Control Register MOTOROLA DSP56367 D-41...

  • Page 474

    SAISR_1 - ESAI_1 Status Register ESAI_1 Y: $FFFF93 Reset $000000 RODF Description Description Receive odd-data register empty REDF Receive odd-data register full Receive even-data register empty Receive even-data register full Description Reserved Description Receive data register empty Description Receive data register full Transmit Frame sync did not occur during word transmission Transmit frame sync occurred during word transmission Description...

  • Page 475

    Channel A Validity (XVA) Channel A User Data (XUA) Channel B Validity (XVB) Channel B User Data (XUB) 15 14 13 12 11 10 9 DAX Non-Audio Data XCB XUB XVB XCA XUA XVA Register (XNADR) X:$FFFFD1 Reset = $00XX00...

  • Page 476

    XBIE DAX Block Trans. Int. Enable XUIE DAX Underrun Int. Enable XDIE Aud. Dat. Reg. Emp. Int. En. Disabled Disabled Disabled Enabled Enabled Enabled XCS1 XCS0 DAX Clock Source DSP Core Clock (f = 1024 x fs) ACI Pin, f = 256 x fs XSB DAX Start Block ACI Pin, f = 384 x fs Disabled...

  • Page 477

    15 14 13 12 11 10 9 Current Value of Prescaler Counter (PC [0:20]) Timer Prescaler Count Register = Reserved, Program as 0 TPCR:$FFFF82 Read Only Reset = $000000 Figure D-30 Timer Prescaler Load and Prescaler Count Registers (TPLR, TPCR) MOTOROLA DSP56367 D-45...

  • Page 478

    = Reserved, Program as 0 TCSR0:$FFFF8F Read/Write Note that for Timers 1 and 2, TC (3:0) = 0000 is the only valid combination. TCSR1:$FFFF8B Read/Write All other combinations are reserved. TCSR2:$FFFF87 Read/Write Reset = $000000 Figure D-31 Timer Control/Status Register D-46 DSP56367 MOTOROLA...

  • Page 479

    19 18 17 16 15 14 13 12 11 10 9 Timer Count Value Timer Count Register TCR0:$FFFF8C Read Only TCR1:$FFFF88 Read Only TCR2:$FFFF84 Read Only Reset = $000000 Figure D-32 Timer Load, Compare and Count Registers MOTOROLA DSP56367 D-47...

  • Page 480

    (HDR) X:$FFFFC9 Read/Write Reset = Undefined Dx holds value of corresponding HDI08 GPIO pin. Function depends on HDDR. See the HDI08 HPCR Register (Figure D-8) for additional Port B GPIO control bits. Figure D-33 GPIO Port B D-48 DSP56367 MOTOROLA...

  • Page 481

    If port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n Figure D-34 GPIO Port C MOTOROLA DSP56367 D-49...

  • Page 482

    If port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n Figure D-35 GPIO Port D D-50 DSP56367 MOTOROLA...

  • Page 483

    If port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n Figure D-36 GPIO Port E MOTOROLA DSP56367 D-51...

  • Page 484

    Programmer’s Reference D-52 DSP56367 MOTOROLA...

  • Page 485

    #$0123FF,x:M_BCR; BCR: Area 3 : 1 w.s (SRAM) ; Default: 1 w.s (SRAM) movep #$0d0000,x:M_PCTL ; XTAL disable ; PLL enable ; CLKOUT disable ; Load the program move #INT_PROG,r0 move #PROG_START,r1 #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ PLOAD_LOOP MOTOROLA DSP56367...

  • Page 486

    YLOAD_LOOP INT_PROG PROG_START move #$0,r0 move #$0,r4 move #$3f,m0 move #$3f,m4 move #$0,x0 move #$0,x1 move #$0,y0 move #$0,y1 bset #4,omr ; ebd #60,_end x0,y0,a x:(r0)+,x1 y:(r4)+,y1 x1,y1,a x:(r0)+,x0 y:(r4)+,y0 x0,y0,a x:(r0)+,x1 x1,y1,a y:(r4)+,y0 move b1,x:$ff _end PROG_END DSP56367 MOTOROLA...

  • Page 487

    $A3662D $A4E762 $84F0F3 $E6F1B0 $B3829 $8BF7AE $63A94F $EF78DC $242DE5 $A3E0BA $EBAB6B $8726C8 $CA361 $2F6E86 $A57347 $4BE774 $8F349D $A1ED12 $4BFCE3 $EA26E0 $CD7D99 $4BA85E $27A43F $A8B10C $D3A55 $25EC6A $2A255B $A5F1F8 $2426D1 $AE6536 $CBBC37 $6235A4 $37F0D $63BEC2 $A5E4D3 $8CE810 $3FF09 $60E50E MOTOROLA DSP56367...

  • Page 488

    $E27540 XDAT_END YDAT_START $5B6DA $C3F70B $6A39E8 $81E801 $C666A6 $46F8E7 $AAEC94 $24233D $802732 $2E3C83 $A43E00 $C2B639 $85A47E $ABFDDF $F3A2C $2D7CF5 $E16A8A $ECB8FB $4BED18 $43F371 $83A556 $E1E9D7 $ACA2C4 $8135AD $2CE0E2 $8F2C73 $432730 $A87FA9 $4A292E $A63CCF $6BA65C $E06D65 $1AA3A $A1B6EB $48AC48 DSP56367 MOTOROLA...

  • Page 489

    Power Consumption Benchmark $EF7AE1 $6E3006 $62F6C7 $6064F4 $87E41D $CB2692 $2C3863 $C6BC60 $43A519 $6139DE $ADF7BF $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF $6162BC $E4A245 YDAT_END MOTOROLA DSP56367...

  • Page 490

    Power Consumption Benchmark DSP56367 MOTOROLA...

  • Page 491

    17 hsckr ip5b_io 18 qvccl power 19 gnd 20 qvcch power 21 hp12 ip5b_io 22 hp11 ip5b_io 23 hp15 ip5b_io 24 hp14 ip5b_io 25 svcc power 26 sgnd 27 ado ip5b_io 28 aci ip5b_io 29 tio ip5b_io MOTOROLA DSP56367...

  • Page 492

    70 aa0 icbc_o 71 bg_ icbc_o 72 eab0 icba_o 73 eab1 icba_o 74 avcc power 75 agnd 76 eab2 icba_o 77 eab3 icba_o 78 eab4 icba_o 79 eab5 icba_o 80 avcc power 81 agnd 82 eab6 icba_o DSP56367 MOTOROLA...

  • Page 493

    123 edb17 icba_io 124 edb18 icba_io 125 edb19 icba_io 126 qvccl power 127 qgnd 128 edb20 icba_io 129 dvcc power 130 dgnd 131 edb21 icba_io 132 edb22 icba_io 133 edb23 icba_io 134 irqd_ ip5b_i 135 irqc_ ip5b_i MOTOROLA DSP56367...

  • Page 494

    -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 [Model] ip5b_io Model_type Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF [Voltage Range] 3.3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) DSP56367 MOTOROLA...

  • Page 495

    4.881e-02 6.960e-02 5.100e+00 5.664e-02 4.912e-02 6.983e-02 5.300e+00 5.679e-02 4.795e-02 7.005e-02 5.500e+00 5.693e-02 4.679e-02 7.026e-02 5.700e+00 5.707e-02 4.688e-02 7.049e-02 5.900e+00 5.722e-02 4.700e-02 7.074e-02 6.100e+00 5.741e-02 4.712e-02 7.105e-02 6.300e+00 5.766e-02 4.723e-02 7.147e-02 6.500e+00 5.801e-02 4.733e-02 7.205e-02 6.600e+00 5.824e-02 4.737e-02 7.242e-02 MOTOROLA DSP56367...

  • Page 496

    -9.25e+01 -7.73e+00 4.900e+00 -9.54e+01 -1.17e+02 -4.18e+01 5.100e+00 -1.38e+02 -1.52e+02 -7.59e+01 5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02 5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02 5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02 5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02 6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 DSP56367 MOTOROLA...

  • Page 497

    3.6v [Pulldown] |voltage I(typ) I(min) I(max) -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 MOTOROLA DSP56367...

  • Page 498

    7.147e-02 6.500e+00 5.801e-02 4.733e-02 7.205e-02 6.600e+00 5.824e-02 4.737e-02 7.242e-02 [Pullup] |voltage I(typ) I(min) I(max) -3.30e+00 2.922e-04 2.177e-04 4.123e-04 -3.10e+00 2.881e-04 2.175e-04 4.021e-04 -2.90e+00 2.853e-04 2.173e-04 3.946e-04 -2.70e+00 2.836e-04 2.172e-04 3.893e-04 -2.50e+00 2.825e-04 2.171e-04 3.857e-04 -2.30e+00 2.819e-04 2.170e-04 3.834e-04 DSP56367 MOTOROLA...

  • Page 499

    -2.63e+02 6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 6.600e+00 -5.21e+02 -4.18e+02 -4.41e+02 [GND_clamp] |voltage I(typ) I(min) I(max) -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 MOTOROLA DSP56367...

  • Page 500

    -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.68e+00 -9.00e-01 -2.70e-02 -1.19e+00 -2.90e-02 -7.00e-01 -1.32e-02 -1.25e-02 -1.63e-02 -5.00e-01 -9.33e-03 -4.69e-03 -1.10e-02 F-10 DSP56367 MOTOROLA...

  • Page 501

    1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.237e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.360e+00 1.444e+01 9.362e+00 -9.00e-01 4.275e-02 2.518e+00 4.663e-02 MOTOROLA DSP56367 F-11...

  • Page 502

    -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 F-12 DSP56367 MOTOROLA...

  • Page 503

    I(min) I(max) dV/dt_r 1.680/0.164 1.360/0.329 1.900/0.124 dV/dt_f 1.690/0.219 1.310/0.442 1.880/0.155 [Model] icba_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF [Voltage Range] 3.3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 MOTOROLA DSP56367 F-13...

  • Page 504

    5.300e+00 1.012e+02 1.006e+02 6.258e+01 5.500e+00 1.270e+02 1.186e+02 8.836e+01 5.700e+00 1.527e+02 1.366e+02 1.141e+02 5.900e+00 1.785e+02 1.546e+02 1.399e+02 6.100e+00 2.043e+02 1.726e+02 1.657e+02 6.300e+00 2.301e+02 1.906e+02 1.915e+02 6.500e+00 2.559e+02 2.086e+02 2.173e+02 6.600e+00 2.688e+02 2.176e+02 2.302e+02 [Pullup] |voltage I(typ) I(min) I(max) F-14 DSP56367 MOTOROLA...

  • Page 505

    5.100e+00 -1.38e+02 -1.52e+02 -7.60e+01 5.300e+00 -1.89e+02 -1.88e+02 -1.11e+02 5.500e+00 -2.40e+02 -2.23e+02 -1.61e+02 5.700e+00 -2.91e+02 -2.59e+02 -2.12e+02 5.900e+00 -3.42e+02 -2.94e+02 -2.63e+02 6.100e+00 -3.93e+02 -3.30e+02 -3.14e+02 6.300e+00 -4.44e+02 -3.65e+02 -3.65e+02 6.500e+00 -4.95e+02 -4.01e+02 -4.16e+02 6.600e+00 -5.21e+02 -4.19e+02 -4.42e+02 [GND_clamp] MOTOROLA DSP56367 F-15...

  • Page 506

    3.554e-02 -7.00e-01 3.426e-04 1.577e-02 9.211e-04 -5.00e-01 2.840e-06 7.857e-05 1.655e-05 -3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) dV/dt_r 1.680/0.164 1.360/0.329 1.900/0.124 dV/dt_f 1.690/0.219 1.310/0.442 1.880/0.155 F-16 DSP56367 MOTOROLA...

  • Page 507

    1.470e-01 3.300e+00 1.078e-01 5.324e-02 1.475e-01 3.500e+00 1.081e-01 5.344e-02 1.479e-01 3.700e+00 1.083e-01 6.705e-02 1.483e-01 3.900e+00 1.086e-01 2.529e+00 1.487e-01 4.100e+00 1.103e-01 1.438e+01 1.491e-01 4.300e+00 1.437e+00 2.638e+01 1.503e-01 4.500e+00 1.800e+01 3.839e+01 1.810e-01 4.700e+00 3.519e+01 5.041e+01 9.452e+00 4.900e+00 5.241e+01 6.419e+01 2.664e+01 MOTOROLA DSP56367 F-17...

  • Page 508

    -1.52e-01 2.900e+00 -1.07e-01 -5.74e-02 -1.54e-01 3.100e+00 -1.08e-01 -5.79e-02 -1.56e-01 3.300e+00 -1.09e-01 -5.84e-02 -1.57e-01 3.500e+00 -1.10e-01 -5.89e-02 -1.59e-01 3.700e+00 -1.11e-01 -6.49e-02 -1.60e-01 3.900e+00 -1.11e-01 -1.23e+00 -1.61e-01 4.100e+00 -1.14e-01 -2.16e+01 -1.62e-01 4.300e+00 -4.76e-01 -4.52e+01 -1.64e-01 4.500e+00 -2.73e+01 -6.89e+01 -1.73e-01 F-18 DSP56367 MOTOROLA...

  • Page 509

    1.135e+02 -1.90e+00 8.778e+01 6.413e+01 8.778e+01 -1.70e+00 6.208e+01 5.035e+01 6.208e+01 -1.50e+00 4.368e+01 3.834e+01 4.368e+01 -1.30e+00 2.649e+01 2.633e+01 2.649e+01 -1.10e+00 9.300e+00 1.433e+01 9.301e+00 -9.00e-01 2.962e-02 2.475e+00 3.075e-02 -7.00e-01 2.501e-04 1.354e-02 6.708e-04 -5.00e-01 2.066e-06 6.280e-05 1.204e-05 -3.00e-01 2.487e-09 5.128e-07 1.417e-08 MOTOROLA DSP56367 F-19...

  • Page 510

    -3.00e-01 -5.19e-10 -1.91e-07 -2.57e-09 -1.00e-01 -1.91e-11 -2.47e-09 -2.19e-11 0.000e+00 -1.68e-11 -1.17e-09 -1.84e-11 [POWER_clamp] |voltage I(typ) I(min) I(max) -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 F-20 DSP56367 MOTOROLA...

  • Page 511

    -4.20e-03 1.000e-01 3.729e-03 1.940e-03 4.177e-03 3.000e-01 1.076e-02 5.578e-03 1.216e-02 5.000e-01 1.723e-02 8.907e-03 1.965e-02 7.000e-01 2.311e-02 1.191e-02 2.663e-02 9.000e-01 2.836e-02 1.455e-02 3.305e-02 1.100e+00 3.292e-02 1.680e-02 3.887e-02 1.300e+00 3.675e-02 1.862e-02 4.404e-02 1.500e+00 3.979e-02 1.997e-02 4.850e-02 1.700e+00 4.205e-02 2.085e-02 5.223e-02 MOTOROLA DSP56367 F-21...

  • Page 512

    2.451e-02 -3.00e-01 1.208e-02 7.503e-03 1.467e-02 -1.00e-01 3.994e-03 2.474e-03 4.868e-03 1.000e-01 -3.88e-03 -2.38e-03 -4.76e-03 3.000e-01 -1.11e-02 -6.76e-03 -1.37e-02 5.000e-01 -1.76e-02 -1.06e-02 -2.20e-02 7.000e-01 -2.35e-02 -1.40e-02 -2.95e-02 9.000e-01 -2.86e-02 -1.69e-02 -3.63e-02 1.100e+00 -3.30e-02 -1.93e-02 -4.23e-02 1.300e+00 -3.65e-02 -2.10e-02 -4.75e-02 F-22 DSP56367 MOTOROLA...

  • Page 513

    -1.30e+00 -4.42e+01 -4.51e+01 -4.16e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.64e+00 -9.00e-01 -7.17e-03 -1.16e+00 -4.87e-03 -7.00e-01 -1.14e-04 -4.39e-03 -3.03e-04 -5.00e-01 -4.86e-07 -2.55e-05 -2.73e-06 -3.00e-01 -5.19e-10 -1.91e-07 -2.57e-09 -1.00e-01 -1.91e-11 -2.47e-09 -2.19e-11 0.000e+00 -1.68e-11 -1.17e-09 -1.84e-11 [POWER_clamp] |voltage I(typ) I(min) I(max) MOTOROLA DSP56367 F-23...

  • Page 514

    -4.67e+02 -2.90e+00 -4.19e+02 -2.95e+02 -4.16e+02 -2.70e+00 -3.68e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.17e+02 -2.24e+02 -3.14e+02 -2.30e+00 -2.66e+02 -1.89e+02 -2.63e+02 -2.10e+00 -2.15e+02 -1.53e+02 -2.12e+02 -1.90e+00 -1.64e+02 -1.18e+02 -1.61e+02 -1.70e+00 -1.14e+02 -9.34e+01 -1.11e+02 -1.50e+00 -7.93e+01 -6.98e+01 -7.68e+01 -1.30e+00 -4.53e+01 -4.62e+01 -4.28e+01 F-24 DSP56367 MOTOROLA...

  • Page 515

    -1.50e+00 4.313e+01 3.766e+01 4.313e+01 -1.30e+00 2.614e+01 2.585e+01 2.614e+01 -1.10e+00 9.145e+00 1.404e+01 9.145e+00 -9.00e-01 1.797e-02 2.364e+00 1.797e-02 -7.00e-01 3.667e-06 7.589e-03 3.667e-06 -5.00e-01 7.730e-10 2.072e-05 7.748e-10 -3.00e-01 2.293e-11 5.767e-08 2.476e-11 -1.00e-01 2.096e-11 1.163e-09 2.278e-11 0.000e+00 2.004e-11 9.618e-10 2.186e-11 [End] MOTOROLA DSP56367 F-25...

  • Page 516

    IBIS Model F-26 DSP56367 MOTOROLA...

  • Page 517: Index

    CP-340, 1-14, 12-1 Digital Audio Transmitter, 2-1, 2-1, 2-20 CPHA and CPOL (HCKR Clock Phase and Polarity Digital Audio Transmitter (DAX), 1-14, 12-1 Controls), 9-10 DIR, 13-10 Divide Factor (DF), 1-9 DMA, 1-9 triggered by timer, 13-24 data ALU, 1-5 MOTOROLA Index-1...

  • Page 518

    HROE (HCSR Host Receive Overrun Error), 9-18 External Memory Expansion Port, 2-6, 3-17 HRQE0-HRQE1 (HCSR Host Request Enable), 9-15 HTDE (HCSR Host Transmit Data Empty), 9-17 HTIE (HCSR Transmit Interrupt Enable), 9-16 HTUE (HCSR Host Transmit Underrun Error), 9-17 functional signal groups, 2-1 Index-2 MOTOROLA...

  • Page 519

    Manual Conventions, iii, iii PLL performance issues, 4-5 maximum ratings, 3-1, 3-2 Port A, 2-1, 2-1, 2-6 mechanical drawings, 14-8 Port B, 2-1, 2-1, 2-11, 2-11, 2-12, 2-12, 7-1 memory Port C, 2-1, 2-1, 2-15, 2-15, 2-19, 7-2, 7-2 MOTOROLA Index-3...

  • Page 520

    Divider Modulus Select, 9-11 read and write accesses, 3-17 Prescaler Rate Select, 9-11 write access, 3-21 HCKR Filter Mode, 9-12 SS, 1-8 HCSR Stack Counter register (SC), 1-8 Bus Error Interrupt Enable, 9-16 Stack Pointer (SP), 1-8 FIFO Enable Control, 9-14 Index-4 MOTOROLA...

  • Page 521

    9—watchdog pulse, 13-22, 13-23 Y Memory Data Bus (YDB), 1-8 modes 11–15—reserved, 13-24 Y Memory Expansion Bus, 1-8 Timer module YAB, 1-9 architecture, 13-1 YDB, 1-8 Timer Prescaler Count Register (TPCR), 13-6 Timer Prescaler Load Register (TPLR), 13-5 MOTOROLA Index-5...

  • Page 522

    Index Index-6 MOTOROLA...

  • Page 524

    (303) 675-2140 Nippon Motorola Ltd. (800) 441-2447 SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Asia/Pacific: Shinagawa-ku, Tokyo, Japan 81-3-5487-8488 Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Internet: Tai Po, N.T., Hong Kong http://www.motorola-dsp.com 852-26629298 DSP56367UM/D Revision 1.0...

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