Icr Double Host Request (Hdrq) Bit 2 - Motorola DSP56367 User Manual

Host Interface (HDI08)
HDI08 – External Host Programmer's Model
In the DMA modes where HDM[2:0]=100 and (HM1≠0 or HM0≠0), TREQ must be set and
RREQ must be cleared to direct DMA transfers from host to DSP. In the other DMA modes,
TREQ is ignored.
Table 8-9 summarizes the effect of RREQ and TREQ on the HOREQ, HTRQ and HRRQ
signals.
Table 8-9 TREQ RREQ Interrupt Mode (HDM[2:0]=000 or HM[1:0]=00)
TREQ RREQ
0 0 No Interrupts (Polling)
0 1 RXDF Request (Interrupt)
1 0 TXDE Request (Interrupt)
1 1 RXDF and TXDE Requests (Interrupts)
Table 8-10 TREQ RREQ DMA Mode (HM1≠0 or HM0≠0)
TREQ RREQ
0 0 No DMA request
0 1 DSP to Host Request (RX)
1 0 Host to DSP Request (TX)
1 1 Reserved
8.6.1.3

ICR Double Host Request (HDRQ) Bit 2

The HDRQ bit determines the functions of the HOREQ/HTRQ and HACK/HRRQ signals as
shown in Table 8-11.
8.6.1.4 ICR Host Flag 0 (HF0) Bit 3
The HF0 bit is used as a general purpose flag for host-to-DSP communication. HF0 may be
set or cleared by the host processor and cannot be changed by the DSP core. HF0 is reflected
in the HSR on the DSP side of the HDI08.
8-22
HDRQ=0
HOREQ signal
HDRQ=0
HOREQ signal
Table 8-11 HDRQ
HDRQ HOREQ/HTRQ pin
0 HOREQ signal
1 HTRQ signal
DSP56367
HDRQ=1
HTRQ signal
No Interrupts (Polling)
No Interrupts (Polling)
TXDE Request (Interrupt)
TXDE Request (Interrupt)
HDRQ=1
HTRQ signal
No DMA request
No DMA request
Host to DSP Request (TX)
Reserved
HACK/HRRQ pin
HACK signal
HRRQ signal
HRRQ signal
No Interrupts (Polling)
RXDF Request (Interrupt)
No Interrupts (Polling)
RXDF Request (Interrupt)
HRRQ signal
No DMA request
DSP to Host Request (RX)
No DMA request
Reserved
MOTOROLA