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8.6.1.5
ICR Host Flag 1 (HF1) Bit 4
The HF1 bit is used as a general purpose flag for host-to-DSP communication. HF1 may be
set or cleared by the host processor and cannot be changed by the DSP core. HF1 is reflected
in the HSR on the DSP side of the HDI08.
8.6.1.6
ICR Host Little Endian (HLEND) Bit 5
If the HLEND bit is cleared, the HDI08 can be accessed by the host in big endian byte order.
If set, the HDI08 can be accessed by the host in little endian byte order. If the HLEND bit is
cleared, the RXH/TXH register is located at address $5, the RXM/TXM register is located at
address $6, and the RXL/TXL register is located at address $7. If the HLEND bit is set, the
RXH/TXH register is located at address $7, the RXM/TXM register is located at address $6,
and the RXL/TXL is located at address $5. See Table 8-8 for an illustration of the effect of
HLEND.
The HLEND function is available only if HDM[2:0]=000 in the host control register (HCR).
When HLEND is available, the ICR bit 6 has no function and should be regarded as reserved.
8.6.1.7
ICR Host Mode Control (HM1 and HM0 bits) Bits 5-6
Bits 6 and 5 function as read/write HM[1:0] bits only when the HCR bits HDM[2:0]=100 (See
Table 8-5). The HM0 and HM1 bits select the transfer mode of the HDI08, as shown in Table
8-12.
When both HM1 and HM0 are cleared, the DMA mode is disabled and the interrupt mode is
enabled. In interrupt mode, the TREQ and RREQ control bits are used for host processor
interrupt control via the external HOREQ output signal, and the HACK input signal is used
for the MC68000 Family vectored interrupt acknowledge input.
When HM1 and/or HM0 are set, they enable the DMA mode and determine the size of the
DMA word to be transferred. In the DMA mode, the HOREQ signal is used to request DMA
transfers, the TREQ and RREQ bits select the direction of DMA transfers (see Table 8-10),
and the HACK input signal is used as a DMA transfer acknowledge input. If the DMA
direction is from DSP to host, the contents of the selected register are enabled onto the host
data bus when HACK is asserted. If the DMA direction is from host to DSP, the selected
register is written from the host data bus when HACK is asserted.
MOTOROLA
Table 8-12 Host Mode Bit Definition
HM1
HM0
0
0
Interrupt Mode (DMA Off)
0
1
DMA Mode (24 Bit)
1
0
DMA Mode (16 Bit)
1
1
DMA Mode (8 Bit)
DSP56367
HDI08 – External Host Programmer's Model
Mode
Host Interface (HDI08)
8-23
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