Host Interface Dsp Core Interrupts - Motorola DSP56367 User Manual

Host Interface (HDI08)
HDI08 – DSP-Side Programmer's Model
is caused by clearing the HEN bit (HPCR bit 6). The stop reset (ST) is caused by executing the
STOP instruction.
Register
Name
HCR
HPCR
HSR
HBAR
HDDR
HDR
HORX HORX[23:0]
HOTX HOTX[23:0]
Note: A long dash (—) denotes that the register value is not affected by the specified reset.
8.5.10

HOST INTERFACE DSP CORE INTERRUPTS

The HDI08 may request interrupt service from either the DSP core or the host processor. The
DSP core interrupts are internal and do not require the use of an external interrupt pin. When
the appropriate interrupt enable bit in the HCR is set, an interrupt condition caused by the host
processor sets the appropriate bit in the HSR, generating an interrupt request to the DSP core.
The DSP core acknowledges interrupts caused by the host processor by jumping to the
appropriate interrupt service routine. The three possible interrupts are as follows:
• Host command
• Transmit data register empty
• Receive data register full
Although there is a set of vectors reserved for host command use, the host command can
access any interrupt vector in the interrupt vector table. The DSP interrupt service routine
8-18
Table 8-7 DSP-Side Registers after Reset
Register
Data
HW
Reset
All bits 0
All bits 0
HF[1:0] 0
HCP 0
HTDE 1
HRDF 0
DMA 0
BA[10:3] $80
DR[15:0] 0
D[15:0] —
empty
empty
DSP56367
Reset Type
SW IR
Reset Reset
0 —
0 —
0 —
0 0
1 1
0 0
0 —
$80 —
0 —
— —
empty empty
empty empty
ST
Reset
—
—
—
0
1
0
—
—
—
—
empty
empty
MOTOROLA