Tcsr Data Input (Di) Bit 12 - Motorola DSP56367 User Manual

an input. The TIO0 signal can be used as a GPIO only when the TC[3:0] bits are all cleared. If
any of the TC[3:0] bits are set, then the GPIO mode is disabled and the DIR bit has no effect.
The DIR bit is cleared by the hardware RESET signal or the software RESET instruction.
This bit is not in use for timers 1 and 2. It should be left cleared.
13.3.4.8

TCSR Data Input (DI) Bit 12

The DI bit reflects the value of the TIO0 signal. If the INV bit is set, the value of the TIO0
signal is inverted before it is written to the DI bit. If the INV bit is cleared, the value of the
TIO0 signal is written directly to the DI bit.
DI is cleared by the hardware RESET signal or the software RESET instruction.
13.3.4.9 TCSR Data Output (DO) Bit 13
The DO bit is the source of the TIO0 value when it is a data output signal. The TIO0 signal is
data output when the GPIO mode is enabled and DIR is set. A value written to the DO bit is
written to the TIO0 signal. If the INV bit is set, the value of the DO bit is inverted when
written to the TIO0 signal. When the INV bit is cleared, the value of the DO bit is written
directly to the TIO0 signal. When GPIO mode is disabled, writing the DO bit has no effect.
The DO bit is cleared by the hardware RESET signal or the software RESET instruction.
This bit is not in use for timers 1 and 2. It should be left cleared.
13.3.4.10 TCSR Prescaler Clock Enable (PCE) Bit 15
The PCE bit is used to select the prescaler clock as the timer source clock. When the PCE bit
is cleared, the timer uses either an internal (CLK/2) signal or an external signal (TIO0) as its
source clock. When the PCE bit is set, the prescaler output is used as the timer source clock
for the counter regardless of the timer operating mode. To ensure proper operation, the PCE
bit should be changed only when the timer is disabled (when the TE bit is cleared). Which
source clock is used for the prescaler is determined by the PS[1:0] bits of the TPLR. Timers 1
and 2 can be clocked by the prescaler clock derived from TIO0.
13.3.4.11 TCSR Timer Overflow Flag (TOF) Bit 20
The TOF bit is set to indicate that counter overflow has occurred. This bit is cleared by writing
a 1 to the TOF bit. Writing a 0 to the TOF bit has no effect. The bit is also cleared when the
timer overflow interrupt is serviced.
The TOF bit is cleared by the hardware RESET signal, the software RESET instruction, the
STOP instruction, or by clearing the TE bit to disable the timer.
MOTOROLA
Timer/Event Counter Programming Model
DSP56367
Timer/ Event Counter
13-11