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DO bit, 13-11
DO loop, 1-8
DRAM, 1-11
out of page
wait states selection guide, 3-33
write access, 3-43
out of page and refresh timings
11 wait states, 3-38
15 wait states, 3-39
4 wait states, 3-33
8 wait states, 3-35
Page mode
read accesses, 3-32
wait states selection guide, 3-22
write accesses, 3-31
Page mode timings
1 wait state, 3-23
2 wait states, 3-24
3 wait states, 3-27
4 wait states, 3-29
refresh access, 3-44
DSP56300 core, 1-2
DSP56300 Family Manual, i, 1-3
DSP56362
specifications, 3-1
E
electrical design considerations, 4-3, 4-3
Enhanced Serial Audio Interface, 2-15, 2-15, 2-19, 2-
19
Enhanced Synchronous Audio Interface, 2-1, 2-1
ESAI, 2-1, 2-1, 2-15, 2-15, 2-19, 2-19
receiver timing, 3-70, 3-70, 3-71, 3-71
timings, 3-66
transmitter timing, 3-69
ESAI block diagram, 10-1
ESSI0 (GPIO), 7-2, 7-2
ESSI1 (GPIO), 7-2
EXTAL jitter, 4-5
external address bus, 2-6
external bus control, 2-6, 2-7, 2-7
external clock operation, 3-6
external data bus, 2-6
external interrupt timing (negative edge-triggered), 3-
15
external level-sensitive fast interrupt timing, 3-14
external memory access (DMA Source) timing, 3-16
External Memory Expansion Port, 2-6, 3-17
F
functional signal groups, 2-1
Index-2
Index
G
Global Data Bus, 1-8
GPIO, 1-12, 2-21
GPIO (ESSI0, Port C), 7-2, 7-2
GPIO (ESSI1, Port D), 7-2
GPIO (HI08, Port B), 7-1
GPIO (Timer), 7-2
GPIO timing, 3-74
Ground, 2-4
ground, 2-1, 2-1
H
HA1, HA3-HA6 (HSAR I
hardware stack, 1-8
HBER (HCSR Bus Error), 9-18
HBIE (HCSR Bus Error Interrupt Enable), 9-16
HBUSY (HCSR Host Busy), 9-18
HCKR (SHI Clock Control Register), 9-9
HCSR
Receive Interrupt Enable Bits, 9-16
SHI Control/Status Register, 9-13
HDI08, 2-1, 2-1, 2-10, 2-12, 2-12, 2-12
HDI08 timing, 3-46
HDM0-HDM5 (HCKR Divider Modulus Select), 9-11
HEN (HCSR SHI Enable), 9-13
HFIFO (HCSR FIFO Enable Control), 9-14
HFM0-HFM1 (HCKR Filter Mode), 9-12
HI08, 1-12
(GPIO), 7-1
2
HI
C
(HCSR
Selection), 9-13
HIDLE (HCSR Idle), 9-15
HM0-HM1 (HCSR Serial Host Interface Mode), 9-13
HMST (HCSR Master Mode), 9-14
Host
Receive Data FIFO (HRX), 9-8
Receive Data FIFO—DSP Side, 9-8
Transmit Data Register (HTX), 9-8
Transmit Data Register—DSP Side, 9-8
Host Interface, 1-12, 2-1, 2-1, 2-10, 2-12, 2-12, 2-12
Host Interface timing, 3-46
HREQ Function In SHI Slave Modes, 9-15
HRFF (HCSR Host Receive FIFO Full), 9-18
HRIE0-HRIE1 (HCSR Receive Interrupt Enable), 9-
16
HRNE (HCSR Host Receive FIFO Not Empty), 9-18
HROE (HCSR Host Receive Overrun Error), 9-18
HRQE0-HRQE1 (HCSR Host Request Enable), 9-15
HTDE (HCSR Host Transmit Data Empty), 9-17
HTIE (HCSR Transmit Interrupt Enable), 9-16
HTUE (HCSR Host Transmit Underrun Error), 9-17
2
C Slave Address), 9-9
Serial
Host
Interface
MOTOROLA
2
I
C/SPI
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