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13.4.2.3
Measurement Input Period (Mode 5)
Bit Settings
TC3
TC2
TC1
0
1
0
In this mode, the timer counts the period between the reception of signal edges of the same
polarity across the TIO0 signal.
Set the TE bit to clear the counter and enable the timer. The value the timer is to count is
loaded into the TLR. The value of the INV bit determines whether the period is measured
between consecutive low-to-high (0 to 1) transitions of TIO0 or between consecutive
high-to-low (1 to 0) transitions of TIO0. If INV is set, high-to-low signal transitions are
selected. If INV is cleared, low-to-high signal transitions are selected.
After the first appropriate transition occurs on the TIO0 input pin, the counter is loaded with
the TLR value on the first timer clock signal received from either the DSP56367 clock divided
by two (CLK/2) or the prescaler clock output. Each subsequent clock signal increments the
counter.
On the next signal transition of the same polarity that occurs on TIO0, the TCF bit in the
TCSR is set and a compare interrupt is generated if the TCIE bit is set. The contents of the
counter are loaded into the TCR. The TCR then contains the value of the time that elapsed
between the two signal transitions on the TIO0 signal.
After the second signal transition, if the TRM bit is set, the TE bit is set to clear the counter
and enable the timer. The counter is repeatedly loaded and incremented until the timer is
disabled. If the TRM bit is cleared, the counter continues to be incremented until it overflows.
This process is repeated until the timer is disabled (i.e., TE is cleared).
If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is
generated.
The counter contents can be read at any time by reading the TCR.
MOTOROLA
TC0
Mode
Name
1
5
Input Period
DSP56367
Timer/ Event Counter
Timer Modes of Operation
Mode Characteristics
Kind
Measurement
TIO0
Clock
Input
Internal
13-19
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