Table of Contents
Advertisement
Timer/ Event Counter
Timer/Event Counter Programming Model
13.3.4.12
TCSR Timer Compare Flag (TCF) Bit 21
The TCF bit is set to indicate that the event count is complete. In the timer, PWM, and
watchdog modes, the TCF bit is set when (N – M + 1) events have been counted (N is the
value in the compare register and M is the TLR value). In the measurement modes, the TCF
bit is set when the measurement has been completed.
The TCF bit is cleared by writing a one into the TCF bit. Writing a zero into the TCF bit has
no effect. The bit is also cleared when the timer compare interrupt is serviced.
The TCF bit is cleared by the hardware RESET signal, the software RESET instruction, the
STOP instruction, or by clearing the TE bit to disable the timer.
Note:
The TOF and TCF bits are cleared by writing a one to the specific bit. In order to
assure that only the desired bit is cleared, do not use the BSET command. The
proper way to clear these bits is to write (using a MOVEP instruction) a one to the
flag to be cleared and a zero to the other flag.
13.3.4.13
TCSR Reserved Bits (Bits 3, 10, 14, 16-19, 22, 23)
These reserved bits are read as zero and should be written with zero for future compatibility.
13.3.5
TIMER LOAD REGISTER (TLR)
The TLR is a 24-bit write-only register. In all modes, the counter is preloaded with the TLR
value after the TE bit in the TCSR is set and a first event occurs. The programmer must
initialize the TLR to ensure correct operation in the appropriate timer operating modes.
•
In timer modes, if the timer reload mode (TRM) bit in the TCSR is set, the counter is
reloaded each time after it has reached the value contained by the timer compare
register (TCR) and the new event occurs.
•
In measurement modes, if the TRM bit in the TCSR is set and the TE bit in the TCSR
is set, the counter is reloaded with the value in the TLR on each appropriate edge of
the input signal.
•
In PWM modes, if the TRM bit in the TCSR is set, the counter is reloaded each time
after it has overflowed and the new event occurs.
•
In watchdog modes, if the TRM bit in the TCSR is set, the counter is reloaded each
time after it has reached the value contained by the TCR and the new event occurs. In
this mode, the counter is also reloaded whenever the TLR is written with a new value
while the TE bit in the TCSR is set.
•
In all modes, if the TRM bit in the TCSR is cleared (TRM = 0), the counter operates as
a free-running counter.
13-12
DSP56367
MOTOROLA
Advertisement
Table of Contents
