Parallel Host Interface (Hdi08) Timing - Motorola DSP56367 User Manual

Specifications

Parallel Host Interface (HDI08) Timing

BG1
BG2
Figure 3-19 Asynchronous Bus Arbitration Timing
Background explanation for Asynchronous Bus Arbitration:
The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and
BB inputs. These synchronization circuits add delay from the external signal until it is
exposed to internal logic. As a result of this delay, a 56300 part may assume mastership and
assert BB for some time after BG is negated. This is the reason for timing 250.
Once BB is asserted, there is a synchronization delay from BB assertion to the time this
assertion is exposed to other 56300 components which are potential masters on the same bus.
If BG input is asserted before that time, a situation of BG asserted, and BB negated, may
cause another 56300 component to assume mastership at the same time. Therefore some
non-overlap period between one BG input active to another BG input active is required.
Timing 251 ensures that such a situation is avoided.
3.11 PARALLEL HOST INTERFACE (HDI08) TIMING
No.
317
Read data strobe assertion width
HACK read assertion width
318
Read data strobe deassertion width
HACK read deassertion width
3-46
Table 3-18 Host Interface (HDI08) Timing
3
Characteristics
4
4
DSP56367
250+251
Expression
T + 9.9
C
—
120 MHz
Unit
Min Max
18.3 — ns
9.9 — ns
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