Hcsr Fifo-Enable Control (Hfifo)—Bit 5 - Motorola DSP56367 User Manual

Serial Host Interface
Serial Host Interface Programming Model
9.5.6.4 HCSR I
The read/write control bit HCKFR determines the behavior of the SHI when the SHI is unable
to service the master request, when operating in the I
2
only in the I C slave mode; it is ignored otherwise.
If HCKFR is set, the SHI holds the clock line to GND if it is not ready to send data to the
master during a read transfer or if the input FIFO is full when the master attempts to execute a
write transfer. In this way, the master may detect that the slave is not ready for the requested
transfer, without causing an error condition in the slave. When HCKFR is set for transmit
sessions, the SHI clock generator must be programmed as if to generate the same serial clock
as produced by the external master, otherwise erroneous operation may result. The
programmed frequency should be in the range of 1 to 0.75 times the external clock frequency.
If HCKFR is cleared, any attempt from the master to execute a transfer when the slave is not
ready results in an overrun or underrun error condition.
It is recommended that an SHI individual reset be generated (HEN cleared) before changing
HCKFR. HCKFR is cleared during hardware reset and software reset.
9.5.6.5 HCSR FIFO-Enable Control (HFIFO)—Bit 5
The read/write control bit HFIFO selects the receive FIFO size. When HFIFO is cleared, the
FIFO has one level. When HFIFO is set, the FIFO has 10 levels. It is recommended that an
SHI individual reset be generated (HEN cleared) before changing HFIFO. HFIFO is cleared
during hardware reset and software reset.
9.5.6.6 HCSR Master Mode (HMST)—Bit 6
The read/write control bit HMST determines the SHI operating mode. If HMST is set, the
interface operates in the master mode. If HMST is cleared, the interface operates in the slave
mode. The SHI supports a single-master configuration in both I
When configured as an SPI master, the SHI drives the SCK line and controls the direction of
the data lines MOSI and MISO. The SS line must be held deasserted in the SPI master mode;
if the SS line is asserted when the SHI is in SPI master mode, a bus error is generated (the
HCSR HBER bit is set—see Section 9.5.6.18).
When configured as an I
clock pulses, and stop events for transmission and reception of serial data.
It is recommended that an SHI individual reset be generated (HEN cleared) before changing
HMST. HMST is cleared during hardware reset and software reset.
9-14
2
C Clock Freeze (HCKFR)—Bit 4
2
C master, the SHI controls the I
DSP56367
2
C slave mode. The HCKFR bit is used
2
C and SPI modes.
2
C bus by generating start events,
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