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Core Configuration
Operating Mode Register (OMR)
6.2
OPERATING MODE REGISTER (OMR)
The contents of the Operating Mode Register (OMR) are shown in Table 6-1. Refer to the
DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication
DSP56300FM/AD for a description of the OMR bits.
Table 6-1 Operating Mode Register (OMR)
SCS
23
22
21
20
19
18
PEN MSW 1: 0 SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CDP1:0 MS SD
PEN
- Patch Enable
MSW1
- Memory switch mode 1
MSW0
- Memory switch mode 0
SEN
- Stack Extension Enable
WRP
- Extended Stack Wrap Flag
EOV
- Extended Stack Overflow
Flag
EUN
- Extended Stack Underflow
Flag
XYS
- Stack Extension Space
Select
- Reserved bit. Read as zero, should be written with zero for future compatibility
6.2.1
ASYNCHRONOUS BUS ARBITRATION ENABLE (ABE) -
BIT 13
The asynchronous bus arbitration mode is activated by setting the ABE bit in the OMR
register. Hardware reset clears the ABE bit.
6.2.2
ADDRESS ATTRIBUTE PRIORITY DISABLE (APD) - BIT 14
The Address Attribute Priority Disable (APD) bit is used to turn off the address attribute
priority mechanism. When this bit is set, more than one address attribute pin AA/RAS(2:0)
may be simultaneously asserted according to its AAR settings. The APD bit is cleared by
hardware reset.
6-2
EOM
17
16
15
14
13
12
ATE
- Address Tracing Enable
APD
- Address Priority Disable
ABE
- Asyn. Bus Arbitration
Enable
BRT
- Bus Release Timing
TAS
- TA Synchronize Select
BE
- Burst Mode Enable
CDP1
- Core-Dma Priority 1
CDP0
- Core-Dma Priority 0
DSP56367
11 10
9
8
7
6
MS
- Master memory Switch Mode
SD
- Stop Delay
EBD
- External Bus Disable
MD
- Operating Mode D
MC
- Operating Mode C
MB
- Operating Mode B
MA
- Operating Mode A
COM
5
4
3
2
1
0
EBD MD MC MB MA
MOTOROLA
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