Interface Control Register (Icr) - Motorola DSP56367 User Manual

8.6.1

INTERFACE CONTROL REGISTER (ICR)

The ICR is an 8-bit read/write control register used by the host processor to control the HDI08
interrupts and flags. The ICR cannot be accessed by the DSP core. The ICR is a read/write
register, which allows the use of bit manipulation instructions on control register bits. The
control bits are described in the following paragraphs.
Bits 2, 5 and 6 of the ICR are affected by the condition of HDM[2:0] (HCR bits 5-7), as
shown in Figure 8-12.
Figure 8-12 Interface Control Register (ICR)
For HDM[2:0]=000
For HDM[2:0]=100
For HDM1=1 and/or
HDM0=1
8.6.1.1 ICR Receive Request Enable (RREQ) Bit 0
In interrupt mode (HDM[2:0]=000 or HM[1:0]=00), RREQ is used to enable host receive data
requests via the host request (HOREQ or HRRQ) signal when the receive data register full
(RXDF) status bit in the ISR is set. If RREQ is cleared, RXDF requests are disabled. If RREQ
is set, the host request signal (HOREQ or HRRQ) is asserted if RXDF is set.
In the DMA modes where HDM[2:0]=100 and (HM1≠0 or HM0≠0), RREQ must be set and
TREQ must be cleared to direct DMA transfers from DSP to host. In the other DMA modes,
RREQ is ignored.
Table 8-9 summarizes the effect of RREQ and TREQ on the HOREQ, HTRQ and HRRQ
signals.
8.6.1.2 ICR Transmit Request Enable (TREQ) Bit 1
In interrupt mode (HDM[2:0]=000 or HM[1:0]=00), TREQ is used to enable host transmit
data requests via the host request (HOREQ or HTRQ) signal when the transmit data register
empty (TXDE) status bit in the ISR is set. If TREQ is cleared, TXDE requests are disabled. If
TREQ is set, the host request signal (HOREQ or HTRQ) is asserted if TXDE is set.
MOTOROLA
7 6 5
INIT HLEND
INIT HM1 HM0
INIT HDM1 HDM0
HDM[1:0] - These read-only bits reflect the value of the HDM[1:0] bits in the HCR.
- Reserved bit. Read as 0. Should be written with 0 for future compatibility.
DSP56367
HDI08 – External Host Programmer's Model
4 3 2
HF1 HF0 HDRQ
HF1 HF0
HF1 HF0
Host Interface (HDI08)
1 0
TREQ RREQ
TREQ RREQ
TREQ RREQ
8-21