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9.5.6.7
HCSR Host-Request Enable (HRQE[1:0])—Bits 8–7
The read/write control bits HRQE[1:0] are used to control the HREQ pin. When HRQE[1:0]
are cleared, the HREQ pin is disabled and held in the high impedance state. If either of
HRQE[1:0] are set and the SHI is in a master mode, the HREQ pin becomes an input
controlling SCK: deasserting HREQ suspends SCK. If either of HRQE[1:0] are set and the
SHI is in a slave mode, HREQ becomes an output and its operation is defined in Table 9-5.
HRQE[1:0] should be changed only when the SHI is idle (HBUSY = 0). HRQE[1:0] are
cleared during hardware reset and software reset.
Table 9-5 HREQ Function In SHI Slave Modes
HRQE1
HRQE0
0
0
1
1
9.5.6.8
HCSR Idle (HIDLE)—Bit 9
The read/write control/status bit HIDLE is used only in the I
otherwise. It is only possible to set the HIDLE bit during writes to the HCSR. HIDLE is
cleared by writing to HTX. To ensure correct transmission of the slave device address byte,
HIDLE should be set only when HTX is empty (HTDE = 1). After HIDLE is set, a write to
HTX clears HIDLE and causes the generation of a stop event, a start event, and then the
transmission of the eight MSBs of the data as the slave device address byte. While HIDLE is
cleared, data written to HTX is transmitted as is. If the SHI completes transmitting a word and
there is no new data in HTX, the clock is suspended after sampling ACK. If HIDLE is set
when the SHI completes transmitting a word with no new data in HTX, a stop event is
generated.
HIDLE determines the acknowledge that the receiver sends after correct reception of a byte. If
HIDLE is cleared, the reception is acknowledged by sending a 0 bit on the SDA line at the
ACK clock tick. If HIDLE is set, the reception is not acknowledged (a 1 bit is sent). It is used
to signal an end-of-data to a slave transmitter by not generating an ACK on the last byte. As a
result, the slave transmitter must release the SDA line to allow the master to generate the stop
event. If the SHI completes receiving a word and the HRX FIFO is full, the clock is suspended
before transmitting an ACK. While HIDLE is cleared the bus is busy, that is, the start event
was sent but no stop event was generated. Setting HIDLE causes a stop event after receiving
the current word.
HIDLE is set while the SHI is not in the I
and during hardware reset, software reset and individual reset.
MOTOROLA
0
High impedance
1
Asserted if IOSR is ready to receive a new word
0
Asserted if IOSR is ready to transmit a new word
1
2
I
C: Asserted if IOSR is ready to transmit or receive
SPI: Asserted if IOSR is ready to transmit and receive
2
C master mode, while the chip is in the stop state,
DSP56367
Serial Host Interface Programming Model
HREQ Pin Operation
2
C master mode; it is ignored
Serial Host Interface
9-15
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