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RHCKD=1
F
OSC
RHCKD=0
HCKR
RHCKD
FLAG0 OUT
(SYNC MODE)
SCKR
RCKD
SCKT
TCKD
THCKD
HCKT
THCKD=0
F
OSC
THCKD=1
Figure 10-3 ESAI Clock Generator Functional Block Diagram
MOTOROLA
PRESCALE
DIVIDE BY 1
DIVIDE
BY 2
DIVIDE BY 8
FLAG0 IN
(SYNC MODE)
SYN=1
SYN=0
INTERNAL BIT CLOCK
PRESCALE
DIVIDE BY 1
DIVIDE
BY 2
DIVIDE BY 8
DSP56367
Enhanced Serial Audio Interface (ESAI)
ESAI Programming Model
DIVIDER
DIVIDE BY 1
OR
TO DIVIDE BY
256
RPSR
RPM0 - RPM7
INTERNAL BIT CLOCK
RSWS4-RSWS0
LENGTH DIVIDER
SYN=0
RX SHIFT REGISTER
RCLOCK
SYN=1
TSWS4-TSWS0
TCLOCK
LENGTH DIVIDER
TX SHIFT REGISTER
TPSR
TPM0 - TPM7
DIVIDER
DIVIDE BY 1
OR
TO DIVIDE BY
256
Notes:
1. F
is the DSP56300 Core internal clock
OSC
frequency.
DIVIDER
DIVIDE BY 1
TO DIVIDE BY
16
RFP0 - RFP3
RX WORD
RX WORD
CLOCK
TX WORD
TX WORD
CLOCK
TFP0 - TFP3
DIVIDER
DIVIDE BY 1
TO DIVIDE BY
16
10-11
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