Programming The Serial Clock - Motorola DSP56367 User Manual

Table 3-20 SHI I
No.
Characteristics
187 Last SCL edge to HREQ output not
deasserted
Filters bypassed
Narrow filters enabled
Wide filters enabled
188 HREQ in assertion to first SCL edge
Filters bypassed
Narrow filters enabled
Wide filters enabled
189 First SCL edge to HREQ in not asserted
(HREQ in hold time)
= 1.8 V ± 5%; T
Note: 1. V
CC
2. Pull-up resistor: R
3. Capacitive load: C
4. It is recommended to enable the wide filters when operating in the I
5. It is recommended to enable the narrow filters when operating in the I
3.13.1

PROGRAMMING THE SERIAL CLOCK

The programmed serial clock cycle, T
HRS bits of the HCKR (SHI clock control register).
The expression for T
I
where
– HRS is the prescaler rate select bit. When HRS is cleared, the fixed
divide-by-eight prescaler is operational. When HRS is set, the prescaler is
bypassed.
– HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256
(HDM[7:0] = $00 to $FF) may be selected.
2
In I C mode, the user may select a value for the programmed serial clock cycle from
MOTOROLA
2
C Protocol Timing (Continued)
Symbol/
1,2,3
Expression
T
AS;RQO
×
2 T
C
×
2 T
C
×
2 T
C
T
AS;RQI
×
0.5 T
I
×
0.5 T
t
HO;RQI
= 0°C to +95°C
J
(min) = 1.5 kOhm
P
(max) = 400 pF
b
, is specified by the value of the HDM[7:0] and
2
I CCP
is
2
CCP
× 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
T = [T
2
I CCP C
DSP56367
Serial Host Interface (SHI) I
4
Standard Mode
Min Max
46.7 —
+ 30
96.7 —
+ 80
151.6 —
+ 135
2 -
CCP
4440 —
- 21
C
4373 —
4373 —
0.0 —
Specifications
2
C Protocol Timing
5
Unit
Fast Mode
Min Max
ns
46.7 —
96.7 —
151.6 —
ns
1041 —
999 —
958 —
0.0 — ns
2
C Standard Mode.
2
C Fast Mode.
3-63